公开(公告)号：US12235784B2

公开(公告)日：2025-02-25

申请号：US17823423

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Creston M. Dupree ,  Smruti Subhash Jhaveri ,  Hyun Yoo Lee ,  John Christopher Sancon ,  Kang-Yong Kim ,  Francesco Douglas Verna-Ketel

IPC: G06F13/40 ,  G06F13/16

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, a controller may train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine, using at least one logical operation, bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

公开(公告)号：US12223995B2

公开(公告)日：2025-02-11

申请号：US17823407

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu ,  Hyun Yoo Lee

IPC: G11C11/406 ,  G11C11/4096

Abstract: Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.

公开(公告)号：US12204780B2

公开(公告)日：2025-01-21

申请号：US17660195

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Mark Kalei Hadrick ,  Yu-Sheng Hsu ,  John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu

IPC: G06F3/06

Abstract: Described apparatuses and methods relate to self-refresh arbitration. In a memory system with multiple memory components, an arbiter is configured to manage the occurrence of self-refresh operations. In aspects, the arbiter can receive one or more self-refresh request signals from at least one memory controller for authorization to command one or more memory components to enter a self-refresh mode. Upon receiving the one or more self-refresh request signals, the arbiter, based on a predetermined configuration, can transmit one or more self-refresh enable signals to the at least one memory controller with authorization to command the one or more memory components to enter the self-refresh mode. The configuration can ensure that fewer than all memory components simultaneously enter the self-refresh mode. In so doing, memory components can perform self-refresh operations without exceeding an instantaneous power threshold. The arbiter can be included in, for instance, a Compute Express Link™ (CXL™) memory module.

公开(公告)号：US20240427497A1

公开(公告)日：2024-12-26

申请号：US18741485

申请日：2024-06-12

Applicant: Micron Technology, Inc.

Inventor： Yang Lu

IPC: G06F3/06

Abstract: Apparatuses and methods aggressor queue mitigation based threshold. A memory device detects aggressor rows by changing a count value associated with the row when it is accessed and comparing the count value to a mitigation threshold. Identified aggressor rows are stored in an aggressor queue. The value of the mitigation threshold is set based on a number of addresses which are stored in the aggressor queue. For example the threshold may increase as the number of addresses in the queue increases.

公开(公告)号：US20240411466A1

公开(公告)日：2024-12-12

申请号：US18808887

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Sujeet Ayyapureddi ,  Edmund J. Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Robert M. Walker ,  Danilo Caraccio

IPC: G06F3/06

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

公开(公告)号：US20240404576A1

公开(公告)日：2024-12-05

申请号：US18642144

申请日：2024-04-22

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim ,  Mark Kalei Hadrick

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: Apparatuses and methods for scheduling aspects of usage-based disturbance mitigation based on different external commands are described. An apparatus comprises a memory device, which has at least one bank comprising memory cells. A subset of the memory cells is configured to store data associated with usage-based disturbance. The apparatus includes circuitry configured to mitigate usage-based disturbance within the bank. The memory device is configured to receive, from a memory controller, two commands that are separated in time by a timing offset. The memory device is configured to generate an internal read command based on the first command to cause the memory device to read the data from the subset of the memory cells. The memory device is configured to generate an internal write command based on the second command to cause the memory device to write modified data generated by the circuitry to the subset of the memory cells.

公开(公告)号：US12119043B2

公开(公告)日：2024-10-15

申请号：US17898737

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Edmund Gieske ,  Sujeet Ayyapureddi ,  Yang Lu ,  Amitava Majumdar

IPC: G11C11/4078 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G11C11/40615 ,  G11C11/40618

Abstract: Practical, energy-efficient, and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The mitigation may be implemented on a per-bank basis. The memory media device may be DRAM.

公开(公告)号：US20240338126A1

公开(公告)日：2024-10-10

申请号：US18627859

申请日：2024-04-05

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Yang Lu ,  Wonjun Choi ,  Mark Kalei Hadrick

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0673

Abstract: Apparatuses and techniques for implementing collision avoidance for bank-shared circuitry that supports usage-based disturbance mitigation are described. A memory device includes bank-shared circuitry coupled to multiple banks. The bank-shared circuitry can support usage-based disturbance mitigation. By using the bank-shared circuitry to service multiple banks, the memory device can have a smaller footprint and can be cheaper to manufacture compared to other memory devices with circuitry dedicated for each bank. To avoid conflicts associated with some sequences of commands that may relate to a same bank or different banks and utilize the bank-shared circuitry, the memory controller applies an appropriate timing offset (or delay) between commands. The timing offset allows the memory device time to finish utilizing the bank-shared circuitry for usage-based disturbance mitigation prior to utilizing the bank-shared circuitry in accordance with a subsequent command.

公开(公告)号：US12086270B2

公开(公告)日：2024-09-10

申请号：US18166365

申请日：2023-02-08

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Markus H. Geiger ,  Nathaniel J. Meier

IPC: G06F11/00 ,  G06F21/55 ,  G06F21/57 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50 ,  G11C29/52

CPC classification number: G06F21/577 ,  G06F21/554 ,  G11C8/18 ,  G11C29/022 ,  G11C29/50004 ,  G11C29/52 ,  G06F2221/034 ,  G11C2029/5002

Abstract: There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher-level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.

公开(公告)号：US12074615B2

公开(公告)日：2024-08-27

申请号：US17969856

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Paolo Amato ,  Yang Lu

IPC: H03M13/15 ,  G06F13/42 ,  H03M13/09

CPC classification number: H03M13/152 ,  G06F13/4221 ,  H03M13/095

Abstract: Methods, systems, and devices related to mapping a plurality of pairs of bits of a memory transfer block (MTB) to a plurality of linked (LK) die input/output (LDIO) lines coupling a LK die to an interface (IF) die. The plurality of pairs of bits of the MTB can be communicated from the LK die to the IF die via the plurality of LDIO lines. Responsive to a failure of one of the plurality of LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction can be performed on the pairs of bits mapped to the failed LDIO line. Each of the plurality of pairs of bits is a respective symbol for the BCH error correction.