公开(公告)号：JPS5953940A

公开(公告)日：1984-03-28

申请号：JP16447182

申请日：1982-09-21

Applicant: Nec Corp

Inventor： IWASHITA MASAO

IPC: G06F7/485 ,  G06F7/50 ,  G06F7/508

CPC classification number: G06F7/485 ,  G06F2207/3816

Abstract: PURPOSE:To reduce a quantity of hardware, and to shorten an arithmetic executing time, by executing a double precision adjustment to a high rank side data value and a low rank side data value of a double precision data. CONSTITUTION:An input data value #1 of an input signal 11 and an input data value #2 display an absolute value with a code, by a code 14 and an absolute value 12, and a code 15 and an absolute value 13, respectively. In case when a value of a single precision/double precision arithmetic switching signal 16 is ''0'', when a value of an addition/subtraction designating signal 17 is ''0'', ''1'', addition and subtraction are executed, respectively, between the input signal #1 and #2, and an output signal 19 is generated. When the switching signal 16 is ''1'', subtraction is executed irrespective of a value of the signal 17. Subsequently, with respect to a double precision data by which the input signal #1 is set to the high rank side and the signal #2 is set to the low rank side, a code of the low rank side is made to coincide with a code of the high rank side, processing of carrying-up and carrying-down is executed, and it is outputted. In this case, when an output switching signal 21 is ''0'', the high rank side is outputted, and when siad signal is ''1'', the low rank side is outputted. When the low rank side is being outputted, an input register 1 does not latch the input signal 11 but generates a busy signal 23, and makes an input wait.

Abstract translation: 目的：通过对双精度数据的高排侧数据值和低排侧数据值执行双精度调整，减少硬件数量，缩短运算时间。 构成：输入信号11的输入数据值＃1和输入数据值＃2分别用代码14和绝对值12以及代码15和绝对值13分别显示代码的绝对值。 在单精度/双精度算术切换信号16的值为“0”的情况下，当加减指定信号17的值为“0”，“1”时，相减 分别在输入信号＃1和＃2之间执行，并且产生输出信号19。 当切换信号16为“1”时，执行与信号17的值无关的减法。随后，对于输入信号＃1被设置为高秩侧的双精度数据和信号 将＃2设定为低等级侧，使低级侧的代码与高级侧的代码一致，执行执行和执行的处理，并输出。 在这种情况下，当输出切换信号21为“0”时，输出高级侧，当siad信号为“1”时，输出低级侧。 当输出低级侧时，输入寄存器1不锁存输入信号11，而是产生忙信号23，并进行输入等待。

公开(公告)号：JP2000348177A

公开(公告)日：2000-12-15

申请号：JP16177299

申请日：1999-06-09

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G01B11/30 ,  G01N21/88 ,  G01N21/93 ,  G03F1/84 ,  G06T1/00 ,  G06T7/00

Abstract: PROBLEM TO BE SOLVED: To provide a defect detector which obtains an actual picture of high precision to improve the defect detection sensitivity. SOLUTION: Before inspection, a reticle where a pattern with preliminarily determined dimensions inputted from a picture input means 1 drawn while being shifted by a certain pitch, and a pitch correction table is generated by a correction table generation means 2. At the time of inspection, the pitch correction table generated by the correction table generation means 2 is used, and pitch correction is applied to an input picture by a pitch correction means 3 to correct the pitch distortion, thus reducing false defects to improve the inspection sensitivity.

公开(公告)号：JPS62274346A

公开(公告)日：1987-11-28

申请号：JP11777286

申请日：1986-05-21

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F15/167 ,  G06F9/44 ,  G06F12/00 ,  G06F15/16 ,  G06F15/82

Abstract: PURPOSE:To speed up processing by transferring data independently by a serial and a parallel ports between the cache memory of each processor module and a shared main memory at a request from a data flow processor. CONSTITUTION:Access to a memory space corresponding to address values obtained by connecting high addresses 109 and low addresses 207 in this order viewed from data flow processors 103-106 is enabled. Then, block transfer between a memory 107 and a cache memory 101 is started according to the result of arbitration by sending a request to the memory 107 and performing the arbitration with a request from another processor module when high address values are set in a high address register 201 from the processors 103-106. The memories 101 and 107 have two parallel and serial ports and high-speed transfer is possible.

公开(公告)号：JPS6285343A

公开(公告)日：1987-04-18

申请号：JP22613685

申请日：1985-10-09

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F15/16 ,  G06F9/44 ,  G06F12/00 ,  G06F15/173 ,  G06F15/177 ,  G06F15/82

Abstract: PURPOSE:To execute efficiently the processing by executing continuously read- out from a memory by the designated number of pieces. CONSTITUTION:By the number of continuous read-out data which are sent from a processor part, a data counter 11 is preset, the value of an address register in which a read-out head address is stored in advance is set as an initial value, an increment value which is set in advance is added by an adder 15, and a memory 16 is read out continuously by the designated number of pieces. According to such constitution, a data value 104 which is inputted from an external circuit is inputted to the counter 11, and the memory 16 is brought to read-out.

公开(公告)号：JPS6232552A

公开(公告)日：1987-02-12

申请号：JP17342385

申请日：1985-08-06

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16

Abstract: PURPOSE:To improve an effective access speed by dividing a memory into plural banks, providing independently its each address line and data line, inputting a data synchronizing with a memory cycle, in case when an arrival data does not interfere with each other, and executing simultaneously write to plural backs. CONSTITUTION:A memory access is executed alternately to each bank 18, 19, and in case when a data transfer speed of a bus for transmitting a signal from an external circuit is higher by two times or more than a memory cycle time, an operation is executed most efficiently. A sped of a system clock 129 is set to two times of a speed of memory cycles of the banks 18, 19, respectively. An input address value 101 and a data value 102 are latched to an input register 11 by synchronizing with a rise of a system clock 129, when a busy signal 126 is not being outputted, and become output signals 103, 104, respectively, A partial signal 132 of the signal 103 becomes an input of a gate array 12, and it is used for a switching control of the memory banks 18, 19.

公开(公告)号：JPS61204735A

公开(公告)日：1986-09-10

申请号：JP2114285

申请日：1985-02-06

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F7/00 ,  G06F7/38 ,  G06F7/48 ,  G06F7/483 ,  G06F7/527 ,  G06F7/76 ,  G06F15/82

Abstract: PURPOSE:To execute efficiently and at a high speed a floating point operation on a pipeline of a data driving system by adding a priority encoder circuit, and a circuit of a multiplexer, etc., to an operating circuit of a single precision fixed point. CONSTITUTION:A titled circuit consists of a priority encoder 17 for inputting a signal 118, deriving what ordinal number of bit counted from its uppermost bit position becomes logic '1' first, and outputting a signal 119, a binary decoder 12 fro binary-coding a signal 110 and outputting a signal 112, and a multiplexer 19 for selecting one of signals 107, 108 and outputting a signal 120. Also, this circuit is constituted by containing a multiplexer 18 for inputting the signals 114, 119 and 117, selecting one of them and outputting a signal 121, a multiplexer 13 for selecting one of the signals 110, 112 and outputting 113, and a multiplexer 16 for selecting one of the signals 115, 116 and outputting a signal 118.

公开(公告)号：JPS61134842A

公开(公告)日：1986-06-21

申请号：JP25783984

申请日：1984-12-06

Applicant: Nec Corp

Inventor： IWASHITA MASAO

IPC: G06F15/82 ,  G06F9/44 ,  G06T1/20

Abstract: PURPOSE: To erase the paired data at a time by providing an erasion control circuit which controls the simultaneous erasion of data to be paired with each other in response to the data value and actuating a processor unit according to an instruction set optionally to a parameter table memory in an initialization mode.
CONSTITUTION: A parameter table memory 13 connected to a transfer table memory 12 is connected to an erasion control circuit 15 via a data memory 14. A cue memory 16 connected to the circuit 15 is connected to a processor 17. Then the unit 17 and the memory 12 are connected to a bus interface 11 and then to an external bus. The circuit 15 decides whether a pair of input data values supplied from the memory 14 satisfy the designated conditions or not. Furthermore a signal is delivered to show whether the data satisfying said conditions is valid or invalid. If the invalid is shown, the writing is inhibited to the memory 16.
COPYRIGHT: (C)1986,JPO&Japio

Abstract translation: 目的：通过提供一个擦除控制电路来擦除配对的数据，该控制电路根据数据值来控制数据的同时擦除，并根据指令集可任意地启动一个处理器单元 内存在初始化模式。 构成：连接到转移表存储器12的参数表存储器13经由数据存储器14连接到擦除控制电路15.连接到电路15的提示存储器16连接到处理器17.然后，单元17和 存储器12连接到总线接口11，然后连接到外部总线。 电路15判定从存储器14提供的一对输入数据值是否满足指定条件。 此外，传送信号以显示满足所述条件的数据是有效还是无效。 如果显示无效，写入被禁止到存储器16。