公开(公告)号：JPH02100357A

公开(公告)日：1990-04-12

申请号：JP25268588

申请日：1988-10-06

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE:To make contact parts have high density without feeling a strict limitation of alignment accuracy by forming the contact parts which make contact (cell contact) between each charge storage electrode and each n type diffusion layer in such a self-alignment manner when trench stack capacitor is formed. CONSTITUTION:After polycrystal silicon layer 106' which forms charge electrodes is deposited on the whole face, phosphorus diffuses to the above layer 106' and simultaneously n type diffusion layers 107 are formed on a semiconductor substrate 100. Cell contact between each charge storage electrode and each n type diffusion layer is just made in such a self-alignment manner. Subsequently, anisotropic whole dry etching is performed and charge storage electrodes 106 are formed by leaving the polysilicon layer only at inwall parts of a trench. This configuration eliminates a strict limitation of alignment accuracy and makes contact parts have high density.

公开(公告)号：JPH01150352A

公开(公告)日：1989-06-13

申请号：JP31016287

申请日：1987-12-07

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/10 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PURPOSE:To raise a punch through breakdown strength between memory cells of a superconductor storage device and to prevent software errors from generating by providing a groove in a dielectric isolation region for dividing the element forming regions of the memory cell, and providing a high concentration diffused layer having the same conductivity type as that of a semiconductor substrate of its inner wall. CONSTITUTION:A groove 113 having a predetermined depth is formed on one main surface of a semiconductor substrate 101 made of a P type Si, a P type diffused layer 106 having an impurity concentration, such as 10 /cm is formed by ion implantation into the groove 113, a silicon oxide film 114 is formed by a thermal oxidizing method, the groove is then buried with a polycrystalline Si 107, a field oxide film 102 is provided by a selectively oxidizing method, and a dielectric isolation region is formed. Another groove having a specific depth and diameter of its opening is formed to form a charge storage capacity, an N type diffused layer 105a... having an impurity concentration, such as 10 /cm is formed by ion implantation in the groove, a capacity insulating film 109 is formed on the side face of the groove, the groove is then buried with the polycrystalline Si, and a capacity plate 103 is provided. Subsequently, after a gate insulating film 108 is formed, a gate electrode 104 is formed of the polycrystalline Si. This layer 105a... are conducted with an N type diffused layer 110, the charge of the layer 105a is externally output, thereby reading information.

公开(公告)号：JPH10163433A

公开(公告)日：1998-06-19

申请号：JP31948096

申请日：1996-11-29

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To sufficiently exhibit expected capability of static electricity protecting circuit and improve reliability, by constituting a bipolar transistor forming region in such a manner that the region is not divided by a diode forming region. SOLUTION: N impurity diffusion layers 222 -225 and a P-type semiconductor substrate constitute a parasitic bipolar transistor in a parasitic bipolar transistor forming region 24. N impurity diffusion layers 221 and 222 and P impurity diffusion layers 231 and 232 constitute a diode in a diode forming region 25a. N impurity diffusion layers 226 and 227 and P impurity diffusion layers 223 and 234 constitute a diode in a diode forming region 25b. The parasitic bipolar transistor and the diodes are connected in parallel between a pad 26 for an outer terminal like an I/O terminal and a discharge line 27. Thereby junction deterioration due to excessive current concentration when a junction is broken down is prevented, and a current flows uniformly in the whole of the parasitic bipolar transistor forming region 24, so that stable operation is realized.

公开(公告)号：JPH08241994A

公开(公告)日：1996-09-17

申请号：JP7087695

申请日：1995-03-04

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L29/78

Abstract: PURPOSE: To improve an electrostatic breakdown strength by avoiding a dead space. CONSTITUTION: A first diffused layer 2 connected to an input terminal 1 is provided. A MOS transistor Q1 having a second diffused layer (source region) and the third diffused layer (drain region) in the area of the distance (d) from the first diffused layer 2 is also provided. When this distance (d) is shorter than the predetermined value, a ground wiring layer 8 connected to the ground terminal 7 of one of the second and third diffused layers 4, 5 which is nearer to the first diffused layer 2.

公开(公告)号：JPH07202126A

公开(公告)日：1995-08-04

申请号：JP35316793

申请日：1993-12-29

Applicant: NEC CORP

Inventor： HORIGUCHI YOKO ,  NARITA KAORU

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02

Abstract: PURPOSE:To protect an output transistor and an internal circuit from electrostatic breakdown by a method wherein the parasitic resistance, from the metal terminal in a protective transistor to the first reference potential or the second reference potential, is made smaller than the parasitic resistance from the metal terminal in the output transistor to the first reference potential. CONSTITUTION:An output transistor 22, which controls the potential of an input-output signal, is provided between an output terminal 21, which is the metal terminal used to connect an outer circuit, and the resistor 23 of an inner circuit 201, and a protective transistor 24, with which a discharge path is formed, and a protective diode 25 are provided to protect the inner circuit and the output transistor 22 from a surge current. As the resistance value of the parasitic resistor 202 of the protective transistor is smaller than the resistance value of the parasitic resistor 203 of the output transistor, only the protective transistor, having large current resistivity, is put in operation even when a high voltage pulse is applied to the metal terminal. Accordingly, the most of the surge current is allowed to flow to the protective transistor 24.

公开(公告)号：JPH04365354A

公开(公告)日：1992-12-17

申请号：JP14051991

申请日：1991-06-13

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L23/522 ,  H01L21/768

Abstract: PURPOSE:To provide a structure of a buried type contact which can be manufactured by simplified processes. CONSTITUTION:A wiring structure is formed by a three-layer structure of a metal wiring layer 110, a titanium nitride film 108 and a titanium film 107 and lower two layers are joined only at a contact area and the contact is buried with a burying member 109. Thereby, flattening can be realized and a contact having good junction property and high reliability can be formed. The burying member 109 may be an insulating film or a conductive film and it can preferencially be applied to CMOS because an impurity in the burying member does not diffuse into a diffusion layer 105 due to the barrier property of titanium nitride.

公开(公告)号：JPH04179265A

公开(公告)日：1992-06-25

申请号：JP30767190

申请日：1990-11-14

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE:To realize a 16 Mbit DRAM by forming a capacitor dielectric film, with one-third of the conventional one in thickness and reduced leakage current, to increase capacitance per unit area so that memory cells may be reduced in size. CONSTITUTION:A polysilicon storage electrode 106 is formed on a windowed insulating film 105 formed on a diffused layer 103. A silicon nitride film is formed, and it is then oxidized in an oxygen-steam atmosphere at approximately 900 deg.C to form a silicon oxide film. After the silicon oxide film is removed by wet etching with a solution of hydrofluoric acid, a second silicon oxide film is formed by thermal oxidation in an oxygen-steam atmosphere at approximately 850 deg.C. As a result, a double-layer structure is formed as the dielectric film of a capacitor. A polysilicon film is grown to a thickness of 100nm to form a capacitor electrode 107. The capacitor dielectric thus formed has very few pin holes and weak spots, and good electric characteristics with less leakage.

公开(公告)号：JPH0496363A

公开(公告)日：1992-03-27

申请号：JP21323890

申请日：1990-08-11

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE:To facilitate manufacture even when the lateral direction is shrunk, and to increase the area of the storage electrode of a capacitance section without lowering punch-through breakdown strength by burying one region of source- drain regions combining digit lines into a semiconductor substrate and burying a gate electrode into a trench. CONSTITUTION:The active regions of an element isolation insulating film 102 are partitioned on a P-type semiconductor substrate 101, trenches are formed at centers, silicon is side-etched and masks for forming the trenches are projected, and N-type diffusion regions 106b are shaped through ion implantation. Gate insulating films 103 are formed on the inwalls of the trenches through thermal oxidation, and buried gate electrodes 104 are formed in the trenches in polycrystalline silicon films. The polycrystalline silicon films are formed on the whole surface, and patterned to shape word lines 105, and arsenic ions are implanted to form N type diffusion layers 106a. The N-type diffusion layers 106b constitute digit lines, and tips and the gate electrodes are organized, thus forming a storage electrode by using the whole surface of the semiconductor base body.

公开(公告)号：JPH03155662A

公开(公告)日：1991-07-03

申请号：JP21680690

申请日：1990-08-17

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: PURPOSE:To prevent deterioration peculiar to an LDD due to implantation to a sidewall spacer of hot carriers by forming a P-type diffusion layer to the surface section of an N drain layer just under the sidewall spacer while being separated from a channel region. CONSTITUTION:Sidewall spacers 4, 14 are shaped onto both side faces of gate electrodes 3, 13 respectively. The width of these sidewall spacers 4, 14 is brought to 3000Angstrom from 2000Angstrom . A P channel MOS transistor section is covered with a photo-resist 22, and arsenic ions are implanted by energy of 50keV. Not only the gate electrode 3 but also the sidewall spacers 4 function as masks at that time, and high-concentration N-type drain-source regions 5-2, 6-2 are shaped at both end sections of an active region through self-alignment with the sidewall spacers 4 and an element isolation insulating film 2. The depth of the high- concentration drain-source regions 5-2, 6-2 is brought to 0.3mucm and impurity concentration to 1X10 cm as the result of heat treatment.

公开(公告)号：JP2013168655A

公开(公告)日：2013-08-29

申请号：JP2013041160

申请日：2013-03-01

Applicant: Nec Corp ,  日本電気株式会社

Inventor： NARITA KAORU

IPC: H01L21/822 ,  C01B31/02 ,  H01C7/00 ,  H01L21/336 ,  H01L21/82 ,  H01L27/04 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L27/0629 ,  B82Y10/00 ,  G11C13/025 ,  G11C17/16 ,  G11C17/165 ,  H01C7/006 ,  H01C17/0652 ,  H01L28/22 ,  H01L29/0665 ,  H01L29/0673 ,  H01L51/0018 ,  H01L51/0048 ,  Y10S977/961

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a high-reliability resistor or a carbon nano-tube resistor capable of applying fuse.SOLUTION: A manufacturing method includes a step for preparing an initial solution by throwing a carbon nano-tube into a volatile solvent so as to be a first concentration and applying ultrasonic processing thereto, a step for diluting the initial solution with the volatile solvent step by step while applying ultrasonic processing, adjusting the initial solution to be a second concentration and preparing a coating solution, and a step for applying the coating solution between a first electrode and a second electrode. The first concentration is a concentration equal to or higher than 1×10g/ml and the second concentration is lower than 1×10g/ml.

Abstract translation: 要解决的问题：提供一种制造能够应用熔丝的高可靠性电阻器或碳纳米管电阻器的方法。解决方案：一种制造方法包括通过将碳纳米管投入到制备初始溶液的步骤 挥发性溶剂作为第一浓度并对其进行超声处理，在施加超声波处理的同时，用挥发性溶剂稀释初始溶液的步骤，将初始溶液调节为第二浓度并制备涂布溶液， 在第一电极和第二电极之间施加涂布溶液的步骤。 第一浓度为1×10g / ml以上，第二浓度低于1×10g / ml。