公开(公告)号：BR9906790A

公开(公告)日：2000-10-31

申请号：BR9906790

申请日：1999-01-06

Applicant: QUALCOMM INC

Inventor： KAUFMAN RALPH E ,  APARIN VLADIMIR

IPC: H04L27/34 ,  H03C3/40 ,  H03D3/00 ,  H03D7/16 ,  H04L27/20 ,  H04L27/22 ,  H04L27/36

Abstract: A quadrature modulator and demodulator which provide the requisite level of performance while minimizing power consumption. In the quadrature modulator, the I and Q signals are provided to two pairs of mixers. Each mixer in a pair of mixers modulates an I or Q signal with the respective inphase or quadrature IF sinusoid. The I and Q modulated signals from each pair of mixers are summed. The signals from the summers are provided to a third pair of mixer and modulated with the respective inphase and quadrature RF sinusoids. The signals from the third pair of mixers are summed and provided as the modulated signal. Using this quadrature modulator topology, the amplitude balance and phase error of the modulated signal are made insensitive to the amplitude imbalance and/or phase error of the quadrature splitters used to generate the IF and RF sinusoids. Furthermore, since the first two pairs of mixers and the two subsequent summers are operated at IF frequency, the performance requirements (e.g., bandwidth and linearity) of these components can be ensured while utilizing less power. The inventive concept can be further adopted for use in a quadrature demodulator.

公开(公告)号：CA2360397A1

公开(公告)日：2000-07-20

申请号：CA2360397

申请日：2000-01-13

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H03H7/42 ,  H03F3/45 ,  H03H11/32

Abstract: Many applications require the conversion of a differential current signal in to a single-ended signal. The shortcomings encountered with existing approaches include poor conversion efficiency, limited bandwidth, and large size. The converter disclosed uses active devices to obtain a unit of small size and high efficiency having a wide bandwidth of operation.

公开(公告)号：AU2164500A

公开(公告)日：2000-06-26

申请号：AU2164500

申请日：1999-12-03

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR ,  PERSICO CHARLES K

IPC: H03F1/32 ,  H03H11/28

Abstract: Techniques to reduce intermodulation distortion at the output of an active circuit having even-order and odd-order nonlinearities. The IM3 products generated by the even-order nonlinearity of the active circuit are canceled against the IM3 products generated by the odd-order nonlinearity. The amplitude and phase of the IM3 products can be manipulated by adjusting either the source or load impedance, or both, of the active circuit. The amplitude and phase of the IM2 products generated by the even-order nonlinearity can be manipulated by adjusting the impedance of the active circuit at sub-harmonic and second harmonic frequencies (i.e., the frequencies of the IM2 products). The amplitude and phase of the IM3 products generated by the odd-order nonlinearity can be manipulated by adjusting the impedance of the active circuit at the fundamental frequency. By properly tuning or "matching" the impedance of either the source or load, or both, of the active circuit at either the sub-harmonic or second harmonic frequency, or both, the amplitude and phase of the IM2 products can be adjusted such that the IM3 products resulting from the even-order nonlinearity approximately cancel the IM3 product(s) resulting from the odd-order nonlinearity.

公开(公告)号：CA2316969A1

公开(公告)日：1999-07-15

申请号：CA2316969

申请日：1999-01-06

Applicant: QUALCOMM INC

Inventor： KAUFMAN RALPH E ,  APARIN VLADIMIR

IPC: H04L27/34 ,  H03C3/40 ,  H03D3/00 ,  H03D7/16 ,  H04L27/20 ,  H04L27/22 ,  H04L27/36

Abstract: A quadrature modulator (210) and demodulator (310) which provide the requisite level of performance while minimizing power consumption. In the quadrature modulator (210), the I and Q signals are provided to two pairs of mixers. Each mixer in a pair of mixers modulates an I or Q signal with the respective inphase or quadrature IF sinusoid. The I and Q modulated signals from each pair of mixers are summed. The signals from the summers are provided to a third pair of mixer and modulated with the respective inphase and quadrature RF sinusoids. The signals from the third pair of mixers are summed and provided as the modulated signal. Using this quadrature modulator (210) topology, the amplitude balance and phase error of the modulated signal are made insensitive to the amplitude imbalance and/or phase error of the quadrature splitters used to generate the IF and RF sinusoids. Furthermore, since the first two pairs of mixers and the two subsequent summers are operated at IF frequency, the performance requirements (e.g., bandwidth and linearity) of these components can be ensured while utilizing less power. The inventive concept can be further adopted for use in a quadrature demodulator (310).

公开(公告)号：CA2839279C

公开(公告)日：2017-10-03

申请号：CA2839279

申请日：2012-06-21

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: G06N3/08

Abstract: Certain aspects of the present disclosure support a local competitive learning rule applied in a computational network that leads to sparse connectivity among processing units of the network. The present disclosure provides a modification to the Oja learning rule, modifying the constraint on the sum of squared weights in the Oja rule. This constraining can be intrinsic and local as opposed to the commonly used multiplicative and subtractive normalizations, which are explicit and require the knowledge of all input weights of a processing unit to update each one of them individually. The presented rule provides convergence to a weight vector that is sparser (i.e., has more zero elements) than the weight vector learned by the original Oja rule. Such sparse connectivity can lead to a higher selectivity of processing units to specific features, and it may require less memory to store the network configuration and less energy to operate it.

公开(公告)号：CY1116911T1

公开(公告)日：2017-04-05

申请号：CY151100821

申请日：2015-09-17

Applicant: QUALCOMM INC

Inventor： CICCARELLI STEVEN C ,  BOSSU FREDERIC ,  APARIN VLADIMIR ,  WANG KEVIN H

IPC: H03L7/197 ,  H04B15/06

Abstract: Εντόςενόςδέκτη, ησυχνότηταενόςσήματοςχρονισμούαναφοράςσύγκρισηςπαρεχόμενουσεένανΒρόχομεΚλείδωμαΦάσης (PLL) κλασματικού-Ναλλάζεταιδυναμικάέτσιώστεη ανεπιθύμητηαντίστροφηανάμιξητωναιχμώναναφοράςμεγνωστούςπαρεμβολείς (γιαπαράδειγμα, διαρροήμετάδοσης) ναελαχιστοποιείται. Καθώςτοκανάλιμετάδοσηςαλλάζειεντόςμιαςζώνηςκαικαθώςη συχνότητατηςδιαρροήςμετάδοσηςαλλάζει, ένακύκλωμααλλάζειτηνσυχνότητατουσήματοςχρονισμούαναφοράςσύγκρισηςέτσιώστεοιαιχμέςαναφοράςπαραγόμενεςαπότον PLL ναμετακινούνταισεσυχνότηταέτσιώστεαυτέςναμηναναμιγνύονταιαντίστροφαμετηνδιαρροήτουπομπούσεανεπιθύμητουςτρόπους. Σεμιανδεύτερηάποψη, ο PLL είναιλειτουργίσιμοςείτεωςένας PLL ακέραιου-Νείτεένας PLL 6κλασματικού-Ν. Σεκαταστάσειςχαμηλήςσυνολικήςισχύοςλήψης, ο PLL λειτουργείωςένας PLL ακέραιου-Νγιατηνμείωσητηςεπιδεκτικότηταςτουδέκτησεαιχμέςκλασματικού-Ν. Σεμιαντρίτηάποψη, ηπληροφορίαανίχνευσηςπαρεμβολέαχρησιμοποιείταιγιατονπροσδιορισμότηςσυχνότηταςτουσήματοςχρονισμούαναφοράςσύγκρισης.

公开(公告)号：RU2586864C2

公开(公告)日：2016-06-10

申请号：RU2014101717

申请日：2012-06-21

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: G06N3/08 ,  G06F15/18

Abstract: Группаизобретенийотноситсяк нейроннымсистемами можетбытьиспользованадлялокальногоправиласостязательногообучения, котороедаетв результатеразреженнуюсвязностьсредиблоковобработкисети. Техническимрезультатомявляетсяповышениеэффективностиобучениявычислительнойсети. Способсодержитэтапы, накоторых: вычисляютвыходнойсигналблокаобработкив вычислительнойсетипоменьшеймеречастичнонаоснованиипоменьшеймереодногосуществующеговесаи изменяютпоменьшеймереодинвесблокаобработкис использованиемлокальногоправилаобучения, приэтомлокальноеправилообучениясоздаетразреженнуюсвязностьмеждублокамиобработкивычислительнойсетипосредствомограничениянормывесовоговектора, содержащеговеса, ассоциированныесосвязямимеждублокомобработки, дозаданногозначения. 4 н. и 56 з.п. ф-лы, 11 ил.

公开(公告)号：CA2680521C

公开(公告)日：2015-10-27

申请号：CA2680521

申请日：2008-03-25

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H04B1/525 ,  H04B1/40 ,  H04L27/34

Abstract: This disclosure describes techniques for reducing adverse effects of transmit signal leakage in a full-duplex, wireless communication system. The disclosure describes techniques for reducing adverse effects of second order distortion and cross-modulation distortion of transmit signal leakage from a transmitter via a duplexer. The techniques may be effective in rejecting at least a portion of a transmit leakage signal, thereby reducing or eliminating distortion. The adaptive filter may include an estimator circuit that generates a transmit leakage signal estimate. A summer subtracts the estimate from the received signal to cancel transmit leakage and produce an output signal. The estimator circuit generates the transmit leakage signal estimate based on a reference signal and feedback from the output signal. The reference signal approximates the carrier signal used to generate the transmit signal in the transmitter. The reference signal may be provided by the same oscillator used to produce the transmit carrier signal.

公开(公告)号：IN3106CHN2014A

公开(公告)日：2015-08-14

申请号：IN3106CHN2014

申请日：2014-04-24

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: G06N3/04 ,  G06N3/063

Abstract: Certain aspects of the present disclosure support a technique for utilizing a memory in probabilistic manner to store information about weights of synapses of a neural network.

公开(公告)号：BRPI0809467A2

公开(公告)日：2014-09-09

申请号：BRPI0809467

申请日：2008-03-25

Applicant: QUALCOMM INC

Inventor： APARIN VLADIMIR

IPC: H04B1/52

Abstract: This disclosure describes techniques for reducing adverse effects of transmit signal leakage in a full-duplex, wireless communication system. The disclosure describes techniques for reducing adverse effects of second order distortion and cross-modulation distortion of transmit signal leakage from a transmitter via a duplexer. The techniques may be effective in rejecting at least a portion of a transmit leakage signal, thereby reducing or eliminating distortion. The adaptive filter may include an estimator circuit that generates a transmit leakage signal estimate. A summer subtracts the estimate from the received signal to cancel transmit leakage and produce an output signal. The estimator circuit generates the transmit leakage signal estimate based on a reference signal and feedback from the output signal. The reference signal approximates the carrier signal used to generate the transmit signal in the transmitter. The reference signal may be provided by the same oscillator used to produce the transmit carrier signal.