TIME ACQUISITION IN A WIRELESS POSITION DETERMINATION SYSTEM

    公开(公告)号:CA2440750C

    公开(公告)日:2011-04-26

    申请号:CA2440750

    申请日:2002-03-15

    Applicant: QUALCOMM INC

    Inventor: YOUNIS SAED

    Abstract: A system and method for providing timing information to a wireless device in a position determination system is disclosed. A wireless device includes a reference signal receiver, a signal processor, a wireless communications transceiver and a GPS receiver. The wireless device is adapted to receive a reference signal, extract a snippet of the received reference signal, determine a time o reception for he snippet and transmit the snippet and time of reception to a position determination entity as part of a request for GPS aiding information. The position determination entity includes a timing source, a GPS memory for storing GPS satellite information, a reference signal memory, a communications interface, a signal processor and a control processor. The position determination entity is adapted to continually receive and store a reference signal along with an associated time of reception, and receive the snippet and timestamp transmitted from the wireless device. The position determination entity is further adapted to match the signal snippet to a portion of the stored reference signal, determine a time offset between the timestamp and the time of reception of the matched portion of the stored reference signal, prepare aiding information for the wireless device, synchronize the aiding information to the wireless device using the time offset, and transmit the synchronized aiding information to the wireless device. The wireless device is further adapted to receive the aiding information, including timing information to assist the wireless device in acquiring the GPS signal.

    22.
    发明专利
    未知

    公开(公告)号:AT492941T

    公开(公告)日:2011-01-15

    申请号:AT07110669

    申请日:2001-03-02

    Applicant: QUALCOMM INC

    Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

    23.
    发明专利
    未知

    公开(公告)号:DE60137658D1

    公开(公告)日:2009-03-26

    申请号:DE60137658

    申请日:2001-08-07

    Applicant: QUALCOMM INC

    Inventor: YOUNIS SAED

    Abstract: A method and apparatus for calibrating a Base Station and Mobile Station for use in systems that use round trip delay and systems that do not use round trip delay.

    DIGITAL-TO-ANALOG INTERFACE CIRCUIT HAVING ADJUSTABLE TIME RESPONSE

    公开(公告)号:CA2401893C

    公开(公告)日:2008-10-14

    申请号:CA2401893

    申请日:2001-03-02

    Applicant: QUALCOMM INC

    Abstract: An interface circuit for converting a digital signal to an analog signal. The interface circuit includes a time response adjustment circuit, a modulator, and a filter. The time response adjustment circuit receives the digital signal and generates an adjusted signal. The modulator couples to the time response adjustment circuit, receives the adjusted signal, and generates a modulator signal. The filter couples to the modulator, receives the modulator signal, and generates the analog signal. The analog signal has a time response that is modified by the time response adjustment circuit. In an embodiment, the time response adjustment circuit includes a gain element, a delay element, and a summer. The gain element receives and scales the digital signal by a scaling factor. The delay element receives and delays the digital signal by a time delay. The summer couples to the gain element and the delay element, sums the scaled signal from the gain element and the delayed signal from the delay element to generate the adjusted signal.

    25.
    发明专利
    未知

    公开(公告)号:BR0115401A

    公开(公告)日:2005-01-25

    申请号:BR0115401

    申请日:2001-11-14

    Applicant: QUALCOMM INC

    Abstract: Techniques to detect whether or not a remote terminal is under the coverage of a repeater within a wireless communication network, which may be based on (1) a list of base stations expected to be received while under the repeater's coverage, (2) the characterized environment of the repeater, and/or (3) the propagation delays for a transmission received at the remote terminal. Additional ambiguity resulting from being under a repeater's coverage may also be accounted for and/or compensated by (1) discarding time measurements from repeated base stations, (2) adjusting the processing for position estimation to account for the additional ambiguity due to the repeater, (3) computing a series of position estimates based on multiple transmissions received from the same originating base station and selecting the best estimate, and/or (4) computing a series of position estimates based on multiple transmissions from multiple originating base stations and selecting the best estimate.

    TRANSMITTER ARCHITECTURES FOR COMMUNICATIONS SYSTEMS

    公开(公告)号:CA2739554A1

    公开(公告)日:2001-09-13

    申请号:CA2739554

    申请日:2001-03-02

    Applicant: QUALCOMM INC

    Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

    DIGITAL-TO-ANALOG INTERFACE CIRCUIT HAVING ADJUSTABLE TIME RESPONSE

    公开(公告)号:CA2401893A1

    公开(公告)日:2001-09-13

    申请号:CA2401893

    申请日:2001-03-02

    Applicant: QUALCOMM INC

    Abstract: An interface circuit for converting a digital signal to an analog signal. The interface circuit includes a time response adjustment circuit, a modulator, and a filter. The time response adjustment circuit receives the digital signal and generates an adjusted signal. The modulator couples to the time response adjustment circuit, receives the adjusted signal, and generates a modulator signal. The filter couples to the modulator, receives the modulator signal, and generates the analog signal. The analog signal has a time response that is modified by the time response adjustment circuit. In an embodiment, the time response adjustment circuit includes a gain element, a delay element, and a summer. The gain element receives and scales the digital signal by a scaling factor. The delay element receives and delays the digital signal by a time delay. The summer couples to the gain element and the delay element, sums the scaled signal from the gain element and the delayed signal from the delay element to generate the adjusted signal.

    TRANSMITTER ARCHITECTURES FOR COMMUNICATIONS SYSTEMS

    公开(公告)号:CA2702881C

    公开(公告)日:2015-08-18

    申请号:CA2702881

    申请日:2001-03-02

    Applicant: QUALCOMM INC

    Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or the entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

    TRANSMITTER ARCHITECTURES FOR COMMUNICATIONS SYSTEMS

    公开(公告)号:CA2401891C

    公开(公告)日:2012-01-03

    申请号:CA2401891

    申请日:2001-03-02

    Applicant: QUALCOMM INC

    Abstract: Transmitter architectures for a communications system having improved performance over conventional transmitter architectures. The improvements include a combination of the following: faster response time for the control signals, improved linearity, reduced interference, reduced power consumption, lower circuit complexity, and lower costs. For a cellular application, these improvements can lead to increased system capacity, smaller telephone size, increased talk and standby times, and greater acceptance of the product. Circuitry is provided to speed up the response time of a control signal. The control loop for various elements in the transmit signal path are integrated. A gain control mechanism allows for accurate adjustment of the output transmit power level. Control mechanisms are provided to power down the power amplifier, or th e entire transmit signal path, when not needed. The gains of the various elements in the transmit signal path are controlled to reduce transients in the output transmit power, and to also ensure that transients are downward.

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