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公开(公告)号：US10687004B1
公开(公告)日：2020-06-16
申请号：US16292806
申请日：2019-03-05
Applicant: Raytheon Company
Inventor： Christian M. Boemler
IPC: H01L27/146 , H04N5/357 , H04N5/378 , H04N5/3745
Abstract: A passive readout circuit for reading out a charge stored on an integration capacitor coupled to a photodiode includes a column bus selectively connectable to the integration capacitor, at least one shield line arranged near the column bus such that a first parasitic capacitance is created between the at least one shield line and the column bus and an amplifier having a first input, a second input and an output. The column is connected to the first input and the at least one shield line is connected to the output of the amplifier.
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公开(公告)号：US20170195595A1
公开(公告)日：2017-07-06
申请号：US14984571
申请日：2015-12-30
Applicant: RAYTHEON COMPANY
Inventor： Christian M. Boemler
CPC classification number: H04N5/3575 , H04N5/3559 , H04N5/37206 , H04N5/37452
Abstract: An imaging system unit cell and method of detecting an image. One example of an imaging system unit cell includes a photodetector configured to generate a photo-current in response to receiving optical radiation, a variable capacitance charge storing circuit in electrical communication with the photodetector and configured to integrate an electrical charge accumulated from the photo-current, a control circuit configured to monitor an integration voltage across the variable capacitance charge storing circuit and adjust a capacitance of the variable capacitance charge storing circuit based on the integration voltage, and an output configured to provide an output voltage based at least in part on the integrated voltage.
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公开(公告)号：US09224768B2
公开(公告)日：2015-12-29
申请号：US13959081
申请日：2013-08-05
Applicant: Raytheon Company
Inventor： John J. Drab , Justin Gordon Adams Wehner , Christian M. Boemler
IPC: H01L27/146 , H01L29/868 , H01L27/144 , H01L31/105
CPC classification number: H01L27/14643 , H01L27/1446 , H01L27/14605 , H01L27/14649 , H01L27/14689 , H01L29/868 , H01L31/105
Abstract: A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.
Abstract translation: 一种半导体结构，具有：硅结构; 以及形成在所述硅结构中的多个横向间隔开的PiN二极管; 并且所述硅结构的表面被配置为减少穿过所述PiN二极管的反向偏置漏电流。 在一个实施例中，栅极电极结构设置在硅结构的表面上，栅极电极结构具有设置在相邻的二极管对之间的部分，栅极结构被偏置以防止通过二极管的漏电流。
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公开(公告)号：US20130278804A1
公开(公告)日：2013-10-24
申请号：US13866066
申请日：2013-04-19
Applicant: RAYTHEON COMPANY
Inventor： Martin S. Denham , Christian M. Boemler
IPC: H04N5/347
CPC classification number: H04N5/347 , H04N5/37455 , Y10T29/49128
Abstract: An imaging system includes an array of pixel cells and a plurality of digital memory elements disposed physically separate from and coupled to the array of pixel cells. Each of the pixel cells includes a photodetector, an electrical storage device coupled to the photodetector, and quantization circuitry coupled to the electrical storage device. The photodetector is configured to generate a photo-current in response to light impinging thereon. The electrical storage device is configured to accumulate an electrical charge from the photo-current. The quantization circuitry is configured to convert the electrical charge into an analog quantization event signal. Each of the digital memory elements is in electrical communication with at least one of the pixel cells and is configured to store a digital value in response to receiving the analog quantization event signal from the at least one of the pixel cells.
Abstract translation: 成像系统包括像素单元阵列和与像素单元阵列物理分离并耦合到像素单元阵列的多个数字存储器元件。 每个像素单元包括光电检测器，耦合到光电检测器的电存储器件，以及耦合到电存储器件的量化电路。 光电检测器被配置为响应于其上的光照射而产生光电流。 电存储装置被配置为从光电流累积电荷。 量化电路被配置为将电荷转换成模拟量化事件信号。 每个数字存储器元件与像素单元中的至少一个电气通信，并且被配置为响应于从至少一个像素单元接收模拟量化事件信号来存储数字值。
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公开(公告)号：US11894670B2
公开(公告)日：2024-02-06
申请号：US17480554
申请日：2021-09-21
Applicant: Raytheon Company
Inventor： Christian M. Boemler
CPC classification number: H02H3/20 , G01J1/44 , G01J2001/0276
Abstract: An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes an integration capacitor configured to integrate the electrical current and generate an integrator voltage. The apparatus further includes an amplifier configured to control a transistor switch coupled in series between the photodetector and the integration capacitor. The apparatus also includes an event detector configured to sense a high-energy event affecting the photodetector. In addition, the apparatus includes a switchable clamp coupled across inputs of the amplifier, where the event detector is configured to close the switchable clamp in response to sensing the high-energy event.
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Patent Agency Ranking
公开(公告)号：US11653112B2
公开(公告)日：2023-05-16
申请号：US17101628
申请日：2020-11-23
Applicant: Raytheon Company
Inventor： Christian M. Boemler
Abstract: A method including collecting analog image data from an imaging array wherein the analog image data includes analog image data from a plurality of imaging pixels and from a plurality of opaque pixels. Each row of the imaging array includes both imaging pixels and opaque pixels. Opaque subtraction is performed in an analog domain, wherein biases determined in the opaque pixels for a given row of the imaging array are subtracted from the analog image data of the imaging pixels of that given row for each row of the imaging array. Performing opaque subtraction includes suppressing outliers in the analog image data from the plurality of opaque pixels. The method includes performing analog to digital conversion (ADC) on the analog image data to produce digital image data for the imaging pixels. ADC is performed after opaque subtraction in the analog domain.
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公开(公告)号：US11561132B2
公开(公告)日：2023-01-24
申请号：US16892430
申请日：2020-06-04
Applicant: RAYTHEON COMPANY
Inventor： Eric J. Beuville , Micky Harris , Ryan Boesch , Christian M. Boemler
Abstract: A pixel includes a detector that changes its operating characteristics based on incident energy, an integration capacitor arranged to discharge stored charge through the detector based on changes in the operating characteristics, and an floating gate injection device disposed between the photo-diode and the integration capacitor that controls flow of the charge from the integration capacitor to the detector. The floating gate injection device has a gate, a source electrically coupled to the detector at a first node, and a drain electrically coupled to the integration capacitor. The gate has a control voltage (VT) stored therein to set to a per-pixel bias gate voltage to control a detector bias voltage of the detector at the first node.
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公开(公告)号：US20220166945A1
公开(公告)日：2022-05-26
申请号：US17101628
申请日：2020-11-23
Applicant: Raytheon Company
Inventor： Christian M. Boemler
Abstract: A method including collecting analog image data from an imaging array wherein the analog image data includes analog image data from a plurality of imaging pixels and from a plurality of opaque pixels. Each row of the imaging array includes both imaging pixels and opaque pixels. Opaque subtraction is performed in an analog domain, wherein biases determined in the opaque pixels for a given row of the imaging array are subtracted from the analog image data of the imaging pixels of that given row for each row of the imaging array. Performing opaque subtraction includes suppressing outliers in the analog image data from the plurality of opaque pixels. The method includes performing analog to digital conversion (ADC) on the analog image data to produce digital image data for the imaging pixels. ADC is performed after opaque subtraction in the analog domain.
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29.发明申请公开(公告)号：US20220020791A1
公开(公告)日：2022-01-20
申请号：US16929620
申请日：2020-07-15
Applicant: RAYTHEON COMPANY
Inventor： Michael J. Batinica , Christian M. Boemler , Paul Bryant
IPC: H01L27/146 , H04N5/355
Abstract: An imaging system includes a light sensor, a pulse detection imaging (PDI) circuit, and an image processing unit. The light sensor generates one or both of an image signal and a pulse signal. The pulse PDI circuit includes a first terminal in signal communication with the light sensor to receive one or both of the image signal and the pulse signal and a second terminal in signal communication with a voltage source. The image processing unit is in signal communication with the PDI circuit to receive one or both of the image signal and the pulse signal and to simultaneously perform imagery and pulse detection based on the image signal and the pulse signal, respectively.
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公开(公告)号：US10917599B2
公开(公告)日：2021-02-09
申请号：US16040780
申请日：2018-07-20
Applicant: Raytheon Company
Inventor： Jehyuk Rhee , Angelika Kononenko , Christian M. Boemler
IPC: H04N5/378 , H04N5/33 , H04N5/3745
Abstract: Methods and apparatus for a dual mode focal plane array having a background module including a first capacitor to integrate a first signal for a first amount of time, wherein the first signal comprises a background signal, and a signal module including a second capacitor to integrate a second signal for a second amount of time, wherein the second signal comprises a signal of interest and the background signal, wherein the first and second capacitors have impedance values in a first ratio, and wherein the first amount of time and the second amount of time define a second ratio corresponding to the first ratio.
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