CODED APERTURE FOCAL PLANE ARRAY USING ALL DETECTORS

    公开(公告)号:US20240187749A1

    公开(公告)日:2024-06-06

    申请号:US18072932

    申请日:2022-12-01

    Abstract: A sensing system includes a focal plane array, a detector dual-input circuit, a detector selector circuit and a select module. The focal plane array includes a plurality of detectors. The detector dual-input circuit combines outputs from the detectors received at a first input channel without outputs received at a second input channel. The detector selector circuit establishes a first signal path between the detectors and the first input channel and a second signal path between the detectors and the second input channel. The detector selector circuit includes a mask that maps the detectors to a first detector group or a second detector group. Based on the mask designation, the select module connects one or more of the detectors to the first signal path to establish the first detector group and connects one or more of the detectors to the second signal path to establish the second detector group.

    Imager having background signal removal

    公开(公告)号:US11546534B2

    公开(公告)日:2023-01-03

    申请号:US17188869

    申请日:2021-03-01

    Abstract: Methods and apparatus for an imaging sensor having background subtraction including integrating photocurrent on a first capacitor, and, after a voltage on the first capacitor reaches a threshold, directing the photocurrent to a second capacitor. The first capacitor can be reset. This can be repeated a given number of times until a value on the second capacitor is read out.

    Wide supply range digital level shifter cell

    公开(公告)号:US10855281B2

    公开(公告)日:2020-12-01

    申请号:US16541546

    申请日:2019-08-15

    Abstract: A wide supply range digital level shifter circuit shifts between a variable desired output voltage ranging from a first voltage level and a second voltage level. The wide supply range digital level shifter circuit includes a latch circuit, a first bleeder circuit, and a second bleeder circuit. The latch circuit receives the first voltage level and the second voltage level, and includes first and second clocked differential switches. The first bleeder circuit is connected between the second voltage rail and the first differential switch and is configured to receive a first digital input voltage. The second bleeder circuit is connected between the second voltage rail and the second differential switch and is configured to receive a second digital input voltage. The first and second bleeder circuits isolate the first and second digital input voltages from the variable desired output voltage.

    HIGH-ENERGY SUPPRESSION FOR INFRARED IMAGERS OR OTHER IMAGING DEVICES

    公开(公告)号:US20230095511A1

    公开(公告)日:2023-03-30

    申请号:US17480554

    申请日:2021-09-21

    Abstract: An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes an integration capacitor configured to integrate the electrical current and generate an integrator voltage. The apparatus further includes an amplifier configured to control a transistor switch coupled in series between the photodetector and the integration capacitor. The apparatus also includes an event detector configured to sense a high-energy event affecting the photodetector. In addition, the apparatus includes a switchable clamp coupled across inputs of the amplifier, where the event detector is configured to close the switchable clamp in response to sensing the high-energy event.

    WIDE SUPPLY RANGE DIGITAL LEVEL SHIFTER CELL

    公开(公告)号:US20200112311A1

    公开(公告)日:2020-04-09

    申请号:US16541546

    申请日:2019-08-15

    Abstract: A wide supply range digital level shifter circuit shifts between a variable desired output voltage ranging from a first voltage level and a second voltage level. The wide supply range digital level shifter circuit includes a latch circuit, a first bleeder circuit, and a second bleeder circuit. The latch circuit receives the first voltage level and the second voltage level, and includes first and second clocked differential switches. The first bleeder circuit is connected between the second voltage rail and the first differential switch and is configured to receive a first digital input voltage. The second bleeder circuit is connected between the second voltage rail and the second differential switch and is configured to receive a second digital input voltage. The first and second bleeder circuits isolate the first and second digital input voltages from the variable desired output voltage.

    Digital unit cell with analog counter element

    公开(公告)号:US09854192B2

    公开(公告)日:2017-12-26

    申请号:US15096572

    申请日:2016-04-12

    CPC classification number: H04N5/3698 G01J1/44 H04N5/37455 H04N5/378

    Abstract: According to one aspect, embodiments herein provide a digital unit cell comprising a photodiode, an integration capacitor, a comparator configured to compare a voltage across the integration capacitor with a threshold voltage and to generate a control signal at a first level each time the voltage across the integration capacitor is greater than the threshold voltage, a charge subtraction circuit configured to receive the control signal at the first level and to discharge accumulated charge on the integration capacitor each time the control signal at the first level is received, at least one analog counter configured to receive the control signal at the first level from the comparator and to decrease a count voltage by a fixed amount each time the control signal at the first level is received from the comparator, and a counter readout circuit configured to provide the count voltage to an image processing circuit.

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