-
-
公开(公告)号：ZA765737B
公开(公告)日：1977-09-28
申请号：ZA765737
申请日：1976-09-24
Applicant: RCA CORP
Inventor： HAFERL P
Abstract: In a vertical deflection circuit in which a capacitor in parallel with a pair of vertical deflection coils is charged by respective decreasing and increasing amounts of horizontal rate energy during respective first and second portions of a vertical scan interval for providing a substantially linear vertical sawtooth current through the vertical coils, a resonant circuit tuned to approximately the horizontal rate is coupled in parallel with the capacitor and a portion thereof is serially coupled with the vertical coils for providing a horizontal rate current component of such a phase in the vertical coils as to correct for top and bottom pincushion distortion.
-
公开(公告)号：BR7600940A
公开(公告)日：1976-09-14
申请号：BR7600940
申请日：1976-02-16
Applicant: RCA CORP
Inventor： HAFERL P
Abstract: First and second controllable switching stages are respectively coupled between a source of horizontal retrace pulses and a capacitor connected across a vertical deflection winding. A modulator is coupled to the switching stages for controlling the timing of conduction thereof relative to the timing of the horizontal retrace pulses. One switching stage charges the capacitor in one polarity with pulses of current of gradually decreasing amplitude and duration during a first portion of the vertical trace interval and the other switching stage charges the capacitor in the opposite polarity with pulses of current of gradually increasing amplitude and duration during a second portion of the vertical trace interval. The capacitor supplies scanning current of first and second polarities to the vertical deflection winding during respective first and second portions of each vertical trace interval.
-
-
公开(公告)号：BR7202863D0
公开(公告)日：1973-05-29
申请号：BR286372
申请日：1972-05-08
Applicant: RCA CORP
Inventor： HAFERL P
Abstract: Burst components of PAL-type encoded signal are retained with modulated subcarrier components as they are processed in 1H delay line assembly and delivered to respective demodulators. Reference oscillation phase to which R-Y demodulator responds is effectively reversed every other line, in response to PAL switch apparatus, in order to provide desired R-Y output in successive lines. Reference oscillation phase to which B-Y demodulator responds is alternated by quadrature switch apparatus between B-Y phase (applied throughout each line interval) and R-Y phase (applied during each inter-line blanking interval). A first gating circuit, coupled to the output of the B-Y demodulator, selects that portion of the B-Y demodulator output developed during the burst interval for passage to integrating and amplifying means in order to develop an AFPC voltage for phase control of the local reference oscillator. A second gating circuit, coupled to the output of the R-Y demodulator, selects that portion of the R-Y demodulator output developed during the burst interval for passage to ACC and color killer circuitry. During color operation (enabled state of bandpass chrominance amplifier) the ACC circuiry develops a control current from the second gating circuit output that adjusts the chrominance amplifier gain in a direction appropriate to maintaining burst amplitude substantially constant at a level set by a manual chroma control. The color killer enables the chrominance amplifier for color operation only when the gated R-Y output indicates by its amplitude the presence of a burst in the received signal and by its polarity the correct switching mode for the PAL switch. Unless such circumstances are present, the color killer disables the chrominance amplifier during each line interval; the killer is keyed, however, to enable the chrominance amplifier during each burst interval so that recovery from the disable state may be effected when appropriate. The color killer circuitry also passes a reset pulse to the PAL switch in the absence of a correct mode indication in the gated R-Y output. The color killer circuitry further serves to control the effectiveness of a subcarrier trap for the receiver's luminance channel, removing the trap during line intervals of monochrome operation.
-
Patent Agency Ranking
公开(公告)号：BR7202450D0
公开(公告)日：1973-05-29
申请号：BR245072
申请日：1972-04-20
Applicant: RCA CORP
Inventor： HAFERL P
Abstract: 1388544 Transistor video amplifiers RCA CORPORATION 24 April 1972 [27 April 1971] 11561/71 Heading H3T The series resistor 32 coupling the output of a transistor amplifier 16 to the input electrode of a CR tube is also included in the feedback path and causes (e.g. by co-operation with the capcitance at collector 18) arc voltage pulses from the tube to arrive at the output of the amplifier after the arrival via the feedback pack at the input. Thus, for positive arc voltages the transistor is conducting by the time the arc voltage reaches the output of the amplifier and damage is prevented. In the circuit shown a second stage 18 is included between the output of transistor 16 and the tube. Negative arc voltages are limited in the feedback path by diode 38 but cause the base of 16 to be saturated and thus both transistors to be conductive when the arc voltage reaches the output. Transistor 40 clamps the black level.
-
公开(公告)号：IN145786B
公开(公告)日：1978-12-23
申请号：IN2214CA1975
申请日：1975-11-20
Applicant: RCA CORP
Inventor： HAFERL P
Abstract: First and second controllable switching stages are respectively coupled between a source of horizontal retrace pulses and a capacitor connected across a vertical deflection winding. A modulator is coupled to the switching stages for controlling the timing of conduction thereof relative to the timing of the horizontal retrace pulses. One switching stage charges the capacitor in one polarity with pulses of current of gradually decreasing amplitude and duration during a first portion of the vertical trace interval and the other switching stage charges the capacitor in the opposite polarity with pulses of current of gradually increasing amplitude and duration during a second portion of the vertical trace interval. The capacitor supplies scanning current of first and second polarities to the vertical deflection winding during respective first and second portions of each vertical trace interval.
-
公开(公告)号：NZ179597A
公开(公告)日：1978-12-18
申请号：NZ17959775
申请日：1975-12-19
Applicant: RCA CORP
Inventor： HAFERL P
Abstract: A deflection circuit wherein coupling capacitors are placed in series with the transformed yoke impedance to reduce capacitance values and voltage ratings of these capacitors. One of the coupling capacitors also serves to integrate a centering current developed by a centering circuit, thereby providing for a relatively uniform direct current component through the yoke windings throughout each horizontal line of scan.
-
公开(公告)号：ZA76883B
公开(公告)日：1977-01-26
申请号：ZA76883
申请日：1976-02-13
Applicant: RCA CORP
Inventor： HAFERL P
Abstract: First and second controllable switching stages are respectively coupled between a source of horizontal retrace pulses and a capacitor connected across a vertical deflection winding. A modulator is coupled to the switching stages for controlling the timing of conduction thereof relative to the timing of the horizontal retrace pulses. One switching stage charges the capacitor in one polarity with pulses of current of gradually decreasing amplitude and duration during a first portion of the vertical trace interval and the other switching stage charges the capacitor in the opposite polarity with pulses of current of gradually increasing amplitude and duration during a second portion of the vertical trace interval. The capacitor supplies scanning current of first and second polarities to the vertical deflection winding during respective first and second portions of each vertical trace interval.
-
公开(公告)号：BR7409602A
公开(公告)日：1976-05-25
申请号：BR960274
申请日：1974-11-18
Applicant: RCA CORP
Inventor： HAFERL P
Abstract: First and second amplifiers which consume varying currents are combined in such a manner as to require a common substantially constant power supply current. An energy storage device coupled to both amplifiers stores energy during periods of low current consumption by the first of the amplifiers. This stored energy is then provided for the second amplifier during periods of high current consumption by the first. A control circuit is provided which allows the first amplifier priority in fulfilling its current requirements.
-
-
-
-
-
-
-
-
-
Search Results
40
records
(took 0.021 seconds)
