公开(公告)号：JPH06112475A

公开(公告)日：1994-04-22

申请号：JP23772392

申请日：1992-08-13

Applicant: SONY CORP

Inventor： UGAJIN RYUICHI ,  HASE ICHIRO ,  NOMOTO KAZUMASA

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/68

Abstract: PURPOSE:To realize a quantum box coupled-element high in degree of freedom of design. CONSTITUTION:Quantum boxes composed of quantum boxes of at least two types different from each other in symmetry properties, for example circular column-shaped quantum boxes and square pole-shaped quantum boxes, are arranged to form a quantum box coupled-element. The quantum boxes are changed in shape, or the square pole-shaped quantum boxes are changed in corresponding angle corresponding to the use of the element, whereby a transition probability due to electrons tunneling between the quantum boxes is controlled. The quantum boxes are changed in relative distance between them, if necessary.

公开(公告)号：JP2007059871A

公开(公告)日：2007-03-08

申请号：JP2006118835

申请日：2006-04-24

Applicant: Sony Corp ,  ソニー株式会社

Inventor： HASE ICHIRO ,  SAWADA KEN ,  KAMIMURA MASAYA

IPC: H01L21/331 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide a device structure for a semiconductor device containing highly reliable hetero-bipolar transistor which can realize a sufficient reduction of knee voltage (Vk) and facilitate base contact formation.
SOLUTION: A hetero junction type bipolar transistor comprising at least an emitter layer, a base layer and a collector layer (and further, a sub-collector layer) or a semiconductor device having the same as a main component, wherein the emitter layer and the collector layer each has highly doped thin layers 5 and 9 doped in high concentrations, and these highly doped thin layers has higher dopant concentration than that of adjacent semiconductor layers 4, 6, 8, and 10.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种包含高可靠性异双极晶体管的半导体器件的器件结构，其可以实现膝盖电压（Vk）的充分降低并促进基极接触形成。 解决方案：至少包括发射极层，基极层和集电极层（以及亚极集电极层）的异质结型双极晶体管或具有与其相同的主要成分的半导体器件，其中发射极 层和集电极层各自具有以高浓度掺杂的高掺杂薄层5和9，并且这些高掺杂薄层具有比相邻半导体层4,6,8和10的掺杂浓度更高的掺杂剂浓度。 C）2007，JPO＆INPIT

公开(公告)号：JP2004055788A

公开(公告)日：2004-02-19

申请号：JP2002210597

申请日：2002-07-19

Applicant: Sony Corp ,  ソニー株式会社

Inventor： HASE ICHIRO

IPC: H01L29/808 ,  H01L21/285 ,  H01L21/335 ,  H01L21/337 ,  H01L21/338 ,  H01L29/778 ,  H01L29/812

CPC classification number: H01L29/66462 ,  H01L21/28587 ,  H01L29/7785

Abstract: PROBLEM TO BE SOLVED: To provide a power transistor which realizes a complete enhancement operation and is superior in a low distortion/high efficient characteristic.
SOLUTION: A second barrier layer 3 formed of AlGaAs, a channel layer 4 formed of InGaAs, a third barrier layer 12 formed of InGaP, and a first barrier layer 11 formed of AlGaAs, are sequentially laminated on one face of a substrate 1 formed of single crystal GaAs through a buffer layer 2. A relation of x
1 -x
3 ≤0.5*(Eg
3 -Eg
1 ) is realized between the first barrier layer 11 and the third barrier layer 12 when an electron affinity of the first barrier layer 11 is set to be x
1 , a band gap to be Eg
1 , electron affinity of the third barrier layer 12 to be x
3 , and a band gap to be Eg
3.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2001077378A

公开(公告)日：2001-03-23

申请号：JP24543799

申请日：1999-08-31

Applicant: SONY CORP

Inventor： TSUKAMOTO HIRONORI ,  HASE ICHIRO

IPC: H01L29/80

Abstract: PROBLEM TO BE SOLVED: To obtain an electrostatic induction transistor which is excellent in high-frequency characteristics, increased enough in gate input voltage, and high in mutual conductance. SOLUTION: An N+-type GaAs layer 2 as a first source region, a high electron mobility N-type InGaAs layer 3 as a second source region, an I-type AlGaAs layer 4 as a channel region, an N+-type GaAs layer 5 as a drain region are successively grown on a GaAs substrate 1, the N-type InGaAs layer 3 and the I-type AlGaAs layer 4 are patterned so as to be as wide as prescribed, and the N+-type GaAs layer 5 is patterned into a stripe that is narrower than the patterned layers 3 and 4. Thereafter, Zn is diffused as P-type impurities in a vapor phase into the I-type AlGaAs layer 4, the N-type InGaAs layer 3, and the N+-type GaAs layer 2 located on each side of the stripe-shaped N+-type GaAs layer 5, by which a P+-type region 6 is formed as a gate region for the formation of an electrostatic induction transistor.

公开(公告)号：JPH06252177A

公开(公告)日：1994-09-09

申请号：JP3889893

申请日：1993-02-26

Applicant: SONY CORP

Inventor： HASE ICHIRO

IPC: H01L29/812 ,  H01L21/338 ,  H01L29/778

Abstract: PURPOSE:To realize a FET of a normally off type, by improving its pinch-off characteristic, and to improve its noise characteristic, by improving its source resistance, in the FET made of a compound semiconductor having a high conductivity even in the case of its growth under an undoped condition. CONSTITUTION:In a FET, on at least one surface of a channel layer 1 of a first conductivity type, a barrier layer 2 having a smaller electron affinity than the channel layer 1 wherein an impurity of a second conductivity type is doped is provided.

公开(公告)号：JPH06252160A

公开(公告)日：1994-09-09

申请号：JP5779693

申请日：1993-02-23

Applicant: SONY CORP

Inventor： UGAJIN RYUICHI ,  HASE ICHIRO

IPC: H01L29/205 ,  C04B28/08 ,  H01L21/331 ,  H01L29/73 ,  H01L29/737

Abstract: PURPOSE:To provide a high speed operable transistor with enough electrons existing in the base layer by adopting a multilayer structure in which specific semiconductor layers are formed one by and without the bad effect on the resonant tunnel phenomenon as the emitter and the collector barrier layers are not doped. CONSTITUTION:The title transistor has a structure that a first semiconductor layer 10 of which the lower end energy (Ec) of the conduction band is Ecl, second semiconductor layers 8, 7 of which the Ec and the upper end energy (Ev) of the valence band are Ec2 (on conduction Ec2>Ec1) and Ev2 (on conduction Ev2 Ec3) and Ev4 respectively and a fifth semiconductor layer 2 of which the Ec is Ec5 (on conduction Ec5>Ev4) are formed sequentially. And when the quantization zero level and the quantization first level of the electron of the third semiconductor layer 6 and E0 and E1 respectively, two relations of E0 Ec1 are established.

公开(公告)号：JP2007294782A

公开(公告)日：2007-11-08

申请号：JP2006122846

申请日：2006-04-27

Applicant: Sony Corp ,  ソニー株式会社

Inventor： HASE ICHIRO

IPC: H01L21/331 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device, having an HBT structure (and having the HBT structure as the main constituent), whereby it has an advantage in its low-voltage operation, and the sheet resistance of its base layer is so reduced as to increase its fmax and Gain, and further enables its high-efficiency operation, in particular, its emitter layer can be so formed as to have proper controllability and high quality, and furthermore, its emitter injection efficiency can be obtained stably.
SOLUTION: In the semiconductor device having an HBT (heterojunction bipolar transistor) which has, on a semiconductor substrate, a first conductivity-type emitter layer, a second conductivity-type base layer, and a first conductivity-type collector layer, the main components of the emitter and collector layers are GaAs and the main component of the base layer is Ge.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有HBT结构（并且具有HBT结构作为主要成分）的半导体器件，由此其具有其低电压操作的优点，并且其基极层的薄层电阻 如此降低以增加其fmax和增益，并且进一步使其高效率操作，特别是其发射极层可以形成为具有适当的可控性和高质量，此外，可以稳定地获得其发射体注入效率 。 解决方案：在具有HBT（异质结双极晶体管）的半导体器件中，在半导体衬底上具有第一导电型发射极层，第二导电型基极层和第一导电型集电极层， 发射极和集电极层的主要成分是GaAs，基底层的主要成分是Ge。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2004071669A

公开(公告)日：2004-03-04

申请号：JP2002225631

申请日：2002-08-02

Applicant: Sony Corp ,  ソニー株式会社

Inventor： HASE ICHIRO

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/201 ,  H01L29/205 ,  H01L29/70 ,  H01L29/737 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/7371 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66318

Abstract: PROBLEM TO BE SOLVED: To improve the PA (power amplifier) characteristics of an HBT (heterojunction bipolar transistor).
SOLUTION: A III-V compound semiconductor is employed in which Bi is added to the base layer of a GaAs system HBT or an InP system HBT. A sub collector layer 2 consisting of n
+ -GaAs, a collector layer 3 consisting of n
- -GaAs, a base layer 19 consisting of p
+ -GaAsBi, an emitter layer 5 consisting of n
- -InGaP, a first cap layer 6 consisting of n-GaAs, and a second cap layer 7 consisting of n
+ -InGaAs, are sequentially laminated on a substrate 1 consisting of mono-crystalline GaAs, for example, to constitute the GaAS system HBT.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2003347307A

公开(公告)日：2003-12-05

申请号：JP2002148182

申请日：2002-05-22

Applicant: Sony Corp ,  ソニー株式会社

Inventor： HASE ICHIRO

IPC: H01L21/28 ,  H01L21/331 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To increase the operational speed and the withstanding voltage of a heterojunction bipolar transistor, by making possible an increase in its reliability and reduction in its base resistance.
SOLUTION: The heterojunction bipolar transistor has a first emitter layer 26 formed on a base layer 25 wherein the sum of its electron affinity and its band gap is larger than the base layer 25, and a second emitter layer 27 formed on the first emitter layer 26 to be added with an n-type impurity. The base layer 25 and the first emitter layer 26 are extended to the direction of a base electrode 30 to interpose the extended first emitter layer 26 between the base electrode 30 and the extended base layer 25. Further, a p-type high-concentration impurity is added partially to the first emitter layer.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：为了提高异质结双极晶体管的工作速度和耐受电压，可以增加其可靠性和降低其基极电阻。 解决方案：异质结双极晶体管具有形成在基极层25上的第一发射极层26，其中电子亲和力和其带隙的和大于基极层25，第二发射极层27形成在第一 发射极层26添加n型杂质。 基极层25和第一发射极层26延伸到基极30的方向，以将延伸的第一发射极层26插入到基极30和延伸的基极层25之间。此外，p型高浓度杂质 被部分地添加到第一发射极层。 版权所有（C）2004，JPO

公开(公告)号：JP2001217257A

公开(公告)日：2001-08-10

申请号：JP2000022023

申请日：2000-01-31

Applicant: SONY CORP

Inventor： HASE ICHIRO

IPC: H01L29/808 ,  H01L21/285 ,  H01L21/335 ,  H01L21/337 ,  H01L29/10 ,  H01L29/772 ,  H01L29/778

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which excludes a difficulty in forming a diffusion layer with high accuracy, in which a Vth control operation is performed easily, in which the influence of a depletion layer on the surface of a semiconductor is reduced, in which the carrier density of a channel layer is ensured, and which restrains an increase in the resistance between a source electrode and a gate electrode. SOLUTION: The semiconductor device is provided with a channel layer 14 which is composed of a semiconductor so as to be used as a current passage between the source electrode and a drain electrode. The semiconductor device is provided with a first barrier layer 15 which is formed on the channel layer 14 so as to be composed of a semiconductor whose electron affinity is smaller than that of the channel layer 14. The semiconductor device is provided with a first gate contact layer 24 which comprises a first-conductivity-type low-resistance region composed of a semiconductor containing a first-conductivity-type impurity at a high concentration, in which the sum of its electron affinity and the band gap is by 1.3 eV or more larger than the electron affinity of the channel layer 14 and which is formed on the first barrier layer 15. The semiconductor device is provided with the source electrode 18 and the drain electrode 19 which are formed on the first barrier layer 15 by sandwiching the gate electrode 20.