公开(公告)号：DE69301885D1

公开(公告)日：1996-04-25

申请号：DE69301885

申请日：1993-08-11

Applicant: SONY CORP

Inventor： UGAJIN RYUICHI ,  HASE ICHIRO ,  NOMOTO KAZUMASA

IPC: H01L29/12

Abstract: A quantum device such as a coupled quantum boxes device and its manufacturing method are disclosed. The quantum device comprises: a semiconductor substrate (1); a plurality of box portions (2,3) made of a first semiconductor (2); and a layer (3) made of a second semiconductor provided on circumferences of the box portions, a plurality of quantum boxes being provided with the box portions and the layer of the second semiconductor. The manufacturing method comprises the steps of: making a plurality of box portions (2) of a first semiconductor (4) on a semiconductor substrate (1); and covering circumferences of the box portions with a layer of a second semiconductor (3), a plurality of quantum boxes being provided with the box portions and the layer of the second semiconductor.

公开(公告)号：GB2406970B

公开(公告)日：2005-12-07

申请号：GB0501132

申请日：2003-07-15

Applicant: SONY CORP

Inventor： HASE ICHIRO

IPC: H01L29/808 ,  H01L21/285 ,  H01L21/335 ,  H01L21/337 ,  H01L21/338 ,  H01L29/778 ,  H01L29/812

公开(公告)号：DE3787542D1

公开(公告)日：1993-11-04

申请号：DE3787542

申请日：1987-02-13

Applicant: SONY CORP

Inventor： KAWAI HIROJI ,  IMANAGA SYUNJI ,  HASE ICHIRO ,  KANEKO KUNIO ,  WATANABE NAOZO

IPC: C23C16/52 ,  G01B11/06

公开(公告)号：CA1302803C

公开(公告)日：1992-06-09

申请号：CA529455

申请日：1987-02-11

Applicant: SONY CORP

Inventor： KAWAI HIROJI ,  IMANAGA SYUNJI ,  HASE ICHIRO ,  KANEKO KUNIO ,  WATANABE NAOZO

IPC: C23C16/52 ,  G01B11/06 ,  H01L21/205

Abstract: A method for vapor deposition includes monitoring of growth of semiconductor layer by way of in-situ monitoring. According to the invention, in-situ monitoring is performed by irradiating light beam onto the surface of the growing layer in a direction nearly perpendicular to the surface. Growth parameters of the layer can be detected by monitoring variation of the light reflected by the surface of the layer. Growth condition in vapor deposition chamber is feedback controlled based on the detected growth parameter.

公开(公告)号：DE69105762T2

公开(公告)日：1995-04-27

申请号：DE69105762

申请日：1991-01-28

Applicant: SONY CORP

Inventor： TAIRA KENICHI ,  HASE ICHIRO ,  KAWAI HIROJI

IPC: H01L29/68 ,  H01L21/331 ,  H01L21/334 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H01L29/76

Abstract: A semiconductor device or a hot electron transistor being constructed such that an InAs base layer (11) is sandwiched between a GaSb emitter barrier layer (12) and a GaInAsSb-system collector barrier layer (13), which results in preventing hot electrons of unnecessarily high energy from being injected into the collector and an avalanche current from being generated, thereby making it possible to improve the saturation characteristics of the device.

公开(公告)号：DE69105762D1

公开(公告)日：1995-01-26

申请号：DE69105762

申请日：1991-01-28

Applicant: SONY CORP

Inventor： TAIRA KENICHI ,  HASE ICHIRO ,  KAWAI HIROJI

IPC: H01L29/68 ,  H01L21/331 ,  H01L21/334 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H01L29/76

Abstract: A semiconductor device or a hot electron transistor being constructed such that an InAs base layer (11) is sandwiched between a GaSb emitter barrier layer (12) and a GaInAsSb-system collector barrier layer (13), which results in preventing hot electrons of unnecessarily high energy from being injected into the collector and an avalanche current from being generated, thereby making it possible to improve the saturation characteristics of the device.

公开(公告)号：DE3787542T2

公开(公告)日：1994-04-28

申请号：DE3787542

申请日：1987-02-13

Applicant: SONY CORP

Inventor： KAWAI HIROJI ,  IMANAGA SYUNJI ,  HASE ICHIRO ,  KANEKO KUNIO ,  WATANABE NAOZO

IPC: C23C16/52 ,  G01B11/06

公开(公告)号：GB2406970A

公开(公告)日：2005-04-13

申请号：GB0501132

申请日：2003-07-15

Applicant: SONY CORP

Inventor： HASE ICHIRO

IPC: H01L29/808 ,  H01L21/285 ,  H01L21/335 ,  H01L21/337 ,  H01L21/338 ,  H01L29/778 ,  H01L29/812

Abstract: A semiconductor device realizing a power transistor capable of operating in a complete enhancement mode and excellent in low-distortion high-efficiency characteristic. Over one side of a substrate (1) of single crystal GaAs, a buffer layer (2), a second barrier layer (3) of AlGaAs, a channel layer (4) of InGaAs, a third barrier layer (12) of InGaP, and a first barrier layer (11) of AlGaAs are formed in this order. The first and third barrier layers (11, 12) satisfy the relation x 1 - x 3 & 0.5*(Eg3 - Eg1) where x 1 is the electron affinity of the first barrier layer (11), Eg1 is the band gap thereof, x 3 is the electron affinity of the third barrier layer (12), and the Eg3 is the band gap thereof.

公开(公告)号：DE69301885T2

公开(公告)日：1996-10-31

申请号：DE69301885

申请日：1993-08-11

Applicant: SONY CORP

Inventor： UGAJIN RYUICHI ,  HASE ICHIRO ,  NOMOTO KAZUMASA

IPC: H01L29/12

Abstract: A quantum device such as a coupled quantum boxes device and its manufacturing method are disclosed. The quantum device comprises: a semiconductor substrate (1); a plurality of box portions (2,3) made of a first semiconductor (2); and a layer (3) made of a second semiconductor provided on circumferences of the box portions, a plurality of quantum boxes being provided with the box portions and the layer of the second semiconductor. The manufacturing method comprises the steps of: making a plurality of box portions (2) of a first semiconductor (4) on a semiconductor substrate (1); and covering circumferences of the box portions with a layer of a second semiconductor (3), a plurality of quantum boxes being provided with the box portions and the layer of the second semiconductor.

公开(公告)号：JP2004335701A

公开(公告)日：2004-11-25

申请号：JP2003129008

申请日：2003-05-07

Applicant: Sony Corp ,  ソニー株式会社

Inventor： HASE ICHIRO

IPC: H01L29/417 ,  H01L21/20 ,  H01L21/331 ,  H01L29/737

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a hetero junction bipolar transistor which can lower thermal resistance while suppressing the deterioration of sheet resistance in a collector retrieving layer, and to provide a method for manufacturing the same.
SOLUTION: In the hetero junction bipolar transistor having a collector layer 12, a base layer 14 and an emitter layer 15 laminated on a substrate 10, the collector retrieving layer (sub-collector layer) 11 has a first composition ratio lattice-matching to the substrate in an entire average, and is modulated in a thickness direction so as to have a second composition ratio higher than the first composition. Further, the composition ratio of the collector retrieving layer 11 has the second composition ratio, and the second composition ratio and a third composition ratio different from the second composition ratio and higher than the first composition ratio in thermal conductivity.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种具有异质结双极晶体管的半导体器件，其能够降低热电阻同时抑制集电体检索层中的薄层电阻的劣化，并提供其制造方法。 解决方案：在集电极层12，基极层14和层叠在基板10上的发射极层15的异质结双极晶体管中，集电体取出层（副集电极层）11具有第一组成比， 与基板整体平均匹配，并且在厚度方向上调制以具有高于第一组成的第二组成比。 此外，集电体回收层11的组成比具有第二组成比，第二组成比和第三组成比不同于第二组成比，高于第一组成比热导率。 版权所有（C）2005，JPO＆NCIPI