公开(公告)号：JPH0650824A

公开(公告)日：1994-02-25

申请号：JP20558592

申请日：1992-07-31

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI

IPC: G01K7/34 ,  G01K13/00 ,  H01L21/66

Abstract: PURPOSE:To measure a temperature distribution with high sensitivity and accurately. CONSTITUTION:On a substrate 21, a first wiring 23 and a second wiring 24 are provided so that they are opposed to each other through a through hole of an insulating film 22 interlaid between the two wirings, and a metal plug 26 is provided in the through hole 25 in such a manner that it connects to the first wiring and forms a gap (g) from the second wiring. A change of the gap (g) due to temperature is measured as a change in capacitance or tunnel current and thereby the temperature is detected.

公开(公告)号：JPH05243179A

公开(公告)日：1993-09-21

申请号：JP7814792

申请日：1992-02-29

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/90

Abstract: PURPOSE:To provide a method of forming a barrier metal layer which is small in dispersion of contact resistance to a base or high thermal resistance, where the barrier metal is provided onto the base and the material of the barrier metal restrained from corroding the base. CONSTITUTION:A barrier metal layer is formed as follows: (a); after an opening 14 is provided to an insulating layer 12 formed on a base 10, a TiSiX layer 16 is formed on the insulating layer 12 and inside the opening 14 through a CVD method. (b); a titanium layer 18 is formed on the TiSiX layer 16 through an ECRCVD method. (c); a TiON layer or a titanium nitride layer 20 is formed on the titanium layer 18. Or (a); a first titanium layer is formed on an insulating layer and inside an opening through a ECRCVD method. (b); a titanium nitride layer or a TiON layer is formed on the first titanium layer through a CVD method. (C); a second titanium layer is formed on the titanium nitride layer or the TiON layer through an ECRCVD method, and a second titanium layer is nitrided.

公开(公告)号：JPH05144747A

公开(公告)日：1993-06-11

申请号：JP33157591

申请日：1991-11-21

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI

IPC: H01L21/205 ,  H01L21/285 ,  H01L21/3205

Abstract: PURPOSE:To uniformly form, on the surface of a semiconductor substrate, the crystal nucleus of a thin film containing a high-melting-point metal by a method wherein a gas decomposition means which decomposes a gas composed of a high-melting-point metal compound is installed and a thin-film raw gas is reduced by using a reducing gas. CONSTITUTION:WF6 is used as a gas composed of a high-melting-point metal compound; a gas decomposition means 50 is first actuated. That is to say, electric power is supplied to a heating means 54; a metal tube 52 is heated. In this state, the WF6 gas is made to flow from a gas introduction part 40. The WF6 gas is reacted with the metal tube 52; it is decomposed; it is adsorbed to the surface of a semiconductor substrate 20 via a shower head 30. Then, a thin-film raw gas composed of WF6, a reducing gas composed of SiH4 and, as required, a carrier gas composed of H2 are supplied form the introduction part 40 to a reaction chamber 10. The SiH4 as the reducing gas is dissociated; an Si-based thin film is formed on the surface of a semiconductor substrate. The Si-based thin film formed on the surface of the semiconductor substrate is reacted immediately with the WF6, the WF6 is reduced, and a thin film composed of tungsten is formed on the surface of the semiconductor substrate.

公开(公告)号：JPH0521381A

公开(公告)日：1993-01-29

申请号：JP16960591

申请日：1991-07-10

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI

IPC: H01L21/203 ,  H01L21/205 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065

Abstract: PURPOSE:To provide a semiconductor manufacturing device, in which a semiconductor substrate can be evenly heated. CONSTITUTION:In a semiconductor manufacturing device, in which a semiconductor substrate (a wafer) 9 placed on a support stage (a suspector) 8 in direct contact with the surface of the support stage 8 is heated to treat via the support stage 8, a low-melting point metal 2 is arranged in the interior of the support stage 8 or in close proximity to the support stage 8 so that heat can be transferred to the support stage 8 and a heating means (a lamp) 6 for dissolving the metal 2 and a means for detecting and controlling the temperature of the metal 2 are provided.

公开(公告)号：JPH04142061A

公开(公告)日：1992-05-15

申请号：JP26451890

申请日：1990-10-02

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI

IPC: H01L21/3205 ,  H01L21/768

Abstract: PURPOSE:To make the coverage of an upper-layer interconnection good, to prevent the upper-layer interconnection from becoming thin at an opening part for interconnection and to prevent a void by a method wherein tungsten is grown selectively on tungsten which is left inside the opening part for interconnection use. CONSTITUTION:A contact hole 11a as an opening part for interconnection is made in an layer insulating film 11 deposited on a silicon substrate 10 and composed of SiO2. After that, a titanium nitride (TiN) film 12 as a close contact layer is applied to be thin; then, blanket tungsten 13A is formed so as to be filled into the contact hole 11a and to be applied onto the layer insulating film 11. The tungsten film 13A and the titanium nitride film 12 are etched back; the tungsten film 13A inside the contact hole 11a is overetched; selective tungsten 13B is grown selectively on the tungsten film 13A; an aluminum interconnection 14 is formed. Thereby, the coverage of an upper-layer interconnection is made good.

公开(公告)号：JPH04125931A

公开(公告)日：1992-04-27

申请号：JP24648490

申请日：1990-09-17

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI ,  MIYAMOTO TAKAAKI

IPC: H01L21/3205 ,  H01L21/768

Abstract: PURPOSE:To form a highly reliable board free from wiring exfoliation, by depositing high melting point metal on the whole surface containing a contact hole, and leaving said metal in the contact hole by performing continuous etching-back. CONSTITUTION:After an impurity diffusion region 10a is formed in a silicon substrate 10, an interlayer insulating film 11 is deposited by a CVD method, and a contact hole 11a is formed on the region 110a. A titanium nitride film 12 as a close contact layer is stuck in the hole 11a and on the insulating film 11. A tungsten film 13 is buried in the hole 11a and deposited on the insulating film 11. Etching-back is performed under specified conditions, and the titanium nitride film 12 is exposed, thereby leaving the tungsten film 13 turning to a cause of wiring cracks in only the contact hole 11a. Hence the exfoliation of high melting point metal on the interlayer insulating film is prevented, and reliability can be improved.

公开(公告)号：JP2015056429A

公开(公告)日：2015-03-23

申请号：JP2013187211

申请日：2013-09-10

Applicant: ソニー株式会社 ,  Sony Corp

Inventor： TOMOTA KATSUHIRO ,  HASEGAWA TOSHIAKI ,  TERAHARA HIROSHI

IPC: H01L21/60 ,  H01L23/12 ,  H05K1/14

Abstract: 【課題】例えば素子を構成する配線を備えた積層構造体を、例えば実装用の基板に確実に固定することができる積層構造体組立体を提供する。【解決手段】積層構造体組立体は、下から、第1の配線31、絶縁層21,22及び第1の基板11が積層された積層構造体10、並びに、第2の配線61が形成された第2の基板51を備えており、絶縁層22の延在部から成る張出し部22A、及び、第1の配線31の端部31Aが、積層構造体10の側面10Aから突出しており、張出し部22Aの下面と第2の基板51とは、光硬化型接着剤層71によって接着されており、第1の配線31の端部31Aと第2の配線61とは、メッキ層62を介して電気的に接続されている。【選択図】図1

Abstract translation: 要解决的问题：提供一种层压结构组件，其能够可靠地固定例如具有构成元件的布线的层压结构，例如安装基板。解决方案：层压结构组件包括：层压结构10，其具有 第一布线31，隔离层21,22和第一基板11，从底部依次层叠; 以及形成有第二布线61的第二基板51。 作为隔离层22的延伸部的延伸部22A和从层叠结构体10的侧面10A突出的第一配线31的端部31A。延伸部22A和第二基板51的底面 通过光固化粘合剂层71粘接。第一布线31的端部31A和第二布线61经由镀层62彼此电连接。

公开(公告)号：JP2014209533A

公开(公告)日：2014-11-06

申请号：JP2013193060

申请日：2013-09-18

Applicant: ソニー株式会社 ,  Sony Corp

Inventor： MIURA TOSHIHITO ,  NAKA TOMOHIDE ,  HASEGAWA TOSHIAKI

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53295 ,  H01L23/552 ,  H01L33/44 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 【課題】基板に形成された複数の積層構造体を分離するための分離溝を形成する際に、分離溝に露出した接続端子部の信頼性が低下することの無い積層構造体を提供する。【解決手段】積層構造体10は、下から、配線32、絶縁層21及び基板11が積層されて成り、積層構造体10の側面10Aから配線32の端部が突出しており、絶縁層21を構成する材料と異なる材料から成る保護層22が、絶縁層21と少なくとも配線32の一部との間に形成されている。【選択図】図6

Abstract translation: 要解决的问题：提供一种层压结构，当形成用于分离形成在基板中的多个层叠结构的分离槽时，防止降低暴露于分离槽的连接端子部分的可靠性。解决方案：层压结构10是 通过从底部层叠配线32，绝缘层21和基板11而形成。 布线32的端部从层压结构体10的侧面10A突出。在绝缘层21和布线的至少一部分之间形成由与构成绝缘层21的材料不同的材料构成的保护层22 32。

公开(公告)号：JP2003332422A

公开(公告)日：2003-11-21

申请号：JP2002136844

申请日：2002-05-13

Applicant: Sony Corp ,  ソニー株式会社

Inventor： TAKAHASHI HIROSHI ,  HASEGAWA TOSHIAKI

IPC: H01L21/768 ,  H01L21/312 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method wherein a wiring trench and a connection hole can be formed in a low permittivity film without using films whose permittivity is high in a part between wiring layers, so that wiring capacitance can be reduced.
SOLUTION: Interlayer insulating films 22, 24 are formed of a low permittivity material whose main component is an organic polymer, and an interlayer insulating film 23 is formed of a low permittivity material whose main component is silicon. By alternately laminating kinds of films different in etching endurance, one interlayer insulating film as substratum which is composed of a low permittivity material has high etching resistance, when the other interlayer insulating film of a low permittivity material is etched, and the interlayer insulating film can be etched by high etching selection ratio to the interlayer insulating film as the substratum. As a result, insertion of a film of high permittivity like the conventional etching stopper layer is unnecessary, and the wiring trench and the contact hole can be formed on the interlayer insulating film.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：为了提供半导体器件及其制造方法，其中可以在低介电常数膜中形成布线沟槽和连接孔，而不使用布线层之间的部分的介电常数高的膜，使得布线 可以减小电容。 解决方案：层间绝缘膜22,24由主要成分为有机聚合物的低介电常数材料形成，层间绝缘膜23由主要成分为硅的低介电常数材料形成。 通过交替地层叠耐蚀性不同的各种薄膜，在低介电常数材料的其他层间绝缘膜被蚀刻时，由低介电常数材料构成的作为底层的层间绝缘膜具有高的耐蚀刻性，并且层间绝缘膜可以 通过高蚀刻选择比蚀刻到作为底层的层间绝缘膜。 结果，不需要像常规蚀刻停止层那样插入高介电常数的膜，并且可以在层间绝缘膜上形成布线沟槽和接触孔。 版权所有（C）2004，JPO

公开(公告)号：JP2003243501A

公开(公告)日：2003-08-29

申请号：JP2002045603

申请日：2002-02-22

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI

IPC: H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which is capable of forming interconnection grooves and connection holes accurately in an interlayer insulation film which uses an organic material. SOLUTION: Over a base film 4 on the surface of a substrate, an organic insulation film 5, a first insulation film 6 which can be etched selectively with respect to the organic insulation film 5, and an inorganic stopper layer 7 are formed in this order. Then, a first resist pattern 8 is formed over the inorganic stopper layer 7. By etching with the first resist pattern 8 as a mask, a connection hole pattern is formed in the inorganic stopper layer 7 and the first insulation film 6. The organic insulation film 5 is etched from above the first resist pattern 8 to form the connection holes 10 which reach the substrate, in the organic insulation film 5 and, at the same time, to completely remove the first resist pattern 8. COPYRIGHT: (C)2003,JPO