公开(公告)号：DE69535502T2

公开(公告)日：2008-01-24

申请号：DE69535502

申请日：1995-10-03

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device having a base (11) or main body on which conductive interconnects (14) are formed. At least the surface of the base is insulative. A first dielectric film (15) is formed so as to cover the conductive interconnects (14). A second dielectric film (16) having a relative dielectric constant smaller than that of the first dielectric film (15) is formed at least between the conductive interconnects (14). The thickness of the second dielectric film (16) between the conductive interconnects (14) is greater than the height (D) of the conductive interconnects by 10-100% in the directions of the height and depth. Films made of a material of a low dielectric constant (21-23) are formed over and under the conductive interconnects (14) via the first dielectric film (15) or equivalent films.

公开(公告)号：DE69112171T2

公开(公告)日：1996-05-02

申请号：DE69112171

申请日：1991-10-30

Applicant: SONY CORP

Inventor： WATANABE HIDETOSHI ,  KOMATSU HIROSHI ,  HASEGAWA TOSHIAKI ,  ISHIMARU TOSHIYUKI

IPC: H01J1/304 ,  H01J1/30 ,  H01J9/02 ,  H01J29/48

Abstract: The field emission type emitter comprises a conductive substrate (101), an insulating film (102) formed on the conductive substrate (101), a cavity (102a) formed in the insulating film (102), a cathode (103) formed on the conductive substrate (101) in the cavity (102a), and a gate electrode (105) formed over the insulating film (102). The gate electrode (105) is preferably made of refractory metal silicide. A polycrystalline silicon film (104) is preferably formed between the gate electrode (105) and the insulating film (102). The side walls of the insualating film in the portion of the cavity (102a) preferably have an inverse tapered shape. In the case where as glass substrate (201 in Fig. 5) is used, a conductive film (203) is formed on the glass substrate through an insulating film (202) and the cathode (205) is formed on the conductive film (203) in the cavity (204a). Low cost manufacturing methods of the field emission type emitter are also disclosed. The invention provides for the advantages that a stable structure of the cathode (103;205) and the gate electrode (105) are achieved such that large area field emission type emitter array flat panel displays can be produced with satisfying long time results.

公开(公告)号：DE69112171D1

公开(公告)日：1995-09-21

申请号：DE69112171

申请日：1991-10-30

Applicant: SONY CORP

Inventor： WATANABE HIDETOSHI ,  KOMATSU HIROSHI ,  HASEGAWA TOSHIAKI ,  ISHIMARU TOSHIYUKI

IPC: H01J1/304 ,  H01J1/30 ,  H01J9/02 ,  H01J29/48

Abstract: The field emission type emitter comprises a conductive substrate (101), an insulating film (102) formed on the conductive substrate (101), a cavity (102a) formed in the insulating film (102), a cathode (103) formed on the conductive substrate (101) in the cavity (102a), and a gate electrode (105) formed over the insulating film (102). The gate electrode (105) is preferably made of refractory metal silicide. A polycrystalline silicon film (104) is preferably formed between the gate electrode (105) and the insulating film (102). The side walls of the insualating film in the portion of the cavity (102a) preferably have an inverse tapered shape. In the case where as glass substrate (201 in Fig. 5) is used, a conductive film (203) is formed on the glass substrate through an insulating film (202) and the cathode (205) is formed on the conductive film (203) in the cavity (204a). Low cost manufacturing methods of the field emission type emitter are also disclosed. The invention provides for the advantages that a stable structure of the cathode (103;205) and the gate electrode (105) are achieved such that large area field emission type emitter array flat panel displays can be produced with satisfying long time results.

公开(公告)号：DE69535502D1

公开(公告)日：2007-07-12

申请号：DE69535502

申请日：1995-10-03

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device having a base (11) or main body on which conductive interconnects (14) are formed. At least the surface of the base is insulative. A first dielectric film (15) is formed so as to cover the conductive interconnects (14). A second dielectric film (16) having a relative dielectric constant smaller than that of the first dielectric film (15) is formed at least between the conductive interconnects (14). The thickness of the second dielectric film (16) between the conductive interconnects (14) is greater than the height (D) of the conductive interconnects by 10-100% in the directions of the height and depth. Films made of a material of a low dielectric constant (21-23) are formed over and under the conductive interconnects (14) via the first dielectric film (15) or equivalent films.

公开(公告)号：JP2004193162A

公开(公告)日：2004-07-08

申请号：JP2002355728

申请日：2002-12-06

Applicant: Sony Corp ,  Toshiba Corp ,  ソニー株式会社 ,  株式会社東芝

Inventor： MIYAJIMA HIDESHI ,  AZUMA KAZUYUKI ,  FUJITA KEIJI ,  HASEGAWA TOSHIAKI ,  TABUCHI KIYOTAKA

IPC: C23C16/42 ,  C23C16/50 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76826 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76825

Abstract: PROBLEM TO BE SOLVED: To prevent a resist which serves as a resist pattern for forming a wiring groove in a dual damascene process of forming vias previously from deteriorating in its resolution.
SOLUTION: An SiCN:H film 4 is formed on a silicon substrate 1 by a plasma CVD method in a first reaction chamber, then the silicon substrate 1 is introduced into a second reaction chamber different from the first reaction chamber, electric discharge is generated in He gas filling the second chamber, and then an SiCO:H film 6 is formed on the SiCN:H film 4 by the plasma CVD method.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2002222860A

公开(公告)日：2002-08-09

申请号：JP2001020457

申请日：2001-01-29

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI

IPC: H01L21/768 ,  H01L21/312 ,  H01L21/316 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To form a multi-level wiring layer of dual damascene structure effectively using a low permittivity film in a via contact layer or a wiring layer. SOLUTION: After a multilayer structure of organic films 14 and 18, and organic SOG films 16 and 20 are formed on a substrate, a silicon oxide film becoming a CMP stopper layer, or an organic SOG film and a silicon nitride film becoming an etching film are formed. Subsequently, a wiring pattern is formed on the silicon nitride film using a resist mask and the resist is ashed. Thereafter, SOG is applied for the purpose of planarization and the effect of level different is eliminated. Furthermore, an SOG material is admixed with resin absorbing the exposure wavelength so that a good resolution can be attained. Contact holes are then patterned and the silicon oxide film, organic films and silicon oxide film are etched sequentially. Finally, the silicon oxide film and the organic films are etched using the silicon nitride film as a mask.

公开(公告)号：JP2001044189A

公开(公告)日：2001-02-16

申请号：JP34963099

申请日：1999-12-09

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI ,  TAGUCHI MITSURU ,  MIYATA KOJI

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, which forms a highly reliable wiring structure by solving the problem at the time of using xerogel or fluororesin for the interlayer insulating film between wirings for reducing the interwiring capacitance, the problem, when misalignment occurs, and others. SOLUTION: This manufacturing method of a semiconductor device, which is equipped with an interlayer insulating film 12 including a xerogel film or a fluororesin, is equipped with a process of forming a first mask 25, which serves as an etching mask at forming of a via contact hole 26 by etching the interlayer insulating film 12, on the interlayer insulating film 12 the layer below which is made of an organic film and the layer above which is made of a xerogel film or a fluororesin film, and a process of forming a second mask 21, which serves as an etching mask at formation of a wiring groove 27 by etching the interlayer insulating film 12 and is made different in material quality from that of the first mask 25, on the first mask 25.

公开(公告)号：JP2000323479A

公开(公告)日：2000-11-24

申请号：JP13353399

申请日：1999-05-14

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI ,  TAGUCHI MITSURU ,  MIYATA KOJI ,  IKEDA KOICHI

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To prevent migration of copper in a copper wiring from an interface between a barrier metal layer and a nitride layer to an interlayer insulating film and thus to prevent the occurrence of a leak current and a short circuit between neighboring wirings, by simply covering the upper surface of the copper wiring formed in a wiring trench via a barrier metal layer with a nitride film. SOLUTION: A semiconductor device having a wiring 24 formed in a recessed portion (wiring trench) 22 formed in an interlayer insulating film 21 has a first barrier layer 23 covering the wiring 24 from under the wiring 24, and a second barrier layer 25 covering the wiring 24 from over the wiring 24, wherein the first barrier layer 23 overlaps the second barrier layer 25.

公开(公告)号：JP2000223486A

公开(公告)日：2000-08-11

申请号：JP2452699

申请日：1999-02-02

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI

IPC: H01L21/768 ,  H01L21/312 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To obtain a layer having an etching stopper function by providing a layer containing silicon oxide by segregating silicon oxide in an organic film composing an insulation film and in the vicinity of the interface thereof. SOLUTION: An insulation film 1 is formed on a substrate 10. The insulation film 1 is composes of an organic film 2 and provided with layers 3, 4 containing a silicon oxide by segregating a silicon oxide in the organic film 2 and in the vicinity of the interface thereof. The layers 3, 4 containing a silicon oxide are formed by segregating a silicon oxide from a material containing a silanol group admixed to an organic material, e.g. a silane coupling agent. An inorganic substance layer 5 may also be provided on the layer 4 containing a silicon oxide by CVD. The inorganic substance layer 5 is formed of a silicon based oxide film, an oxide nitride film or a nitride film, for example.

公开(公告)号：JP2000183059A

公开(公告)日：2000-06-30

申请号：JP36114398

申请日：1998-12-18

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI ,  TAGUCHI MITSURU

IPC: H01L21/768 ,  H01L21/318 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To prevent oxidization of metal wiring and reduction of adhesion thereof, when a silicon nitride-based insulation film is formed on the metal wiring which is made of Cu, etc., and which tends to be oxidized. SOLUTION: An Si-rich lower silicon nitirde-based insulation film 5a than that of the stoichiometric composition of Si3N4 and an N-rich upper silicon nitride-based insulation film 5b than that of the insulation film 5a are formed on a metal wiring 4 in sequence, making them a silicon nitride-based insulation film 5. It is desirable to control the concentration of remaining oxygen in a film formation chamber at 100 ppb or lower, when the insulation film 5 is formed.