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    21.
    发明专利
    未知

    公开(公告)号：DE2513459A1

    公开(公告)日：1975-10-09

    申请号：DE2513459

    申请日：1975-03-26

    Applicant: SONY CORP

    Inventor： MATSUSHITA TAKESHI ,  HAYASHI HISAO ,  AOKI TERUAKI ,  YAMOTO HISAYOSHI ,  KAWANA YOSHIYUKI

    IPC: H01L29/73 ,  G02B6/12 ,  H01L21/283 ,  H01L21/314 ,  H01L21/331 ,  H01L21/76 ,  H01L27/04 ,  H01L29/78 ,  H01L29/861

    Abstract: 1496814 Semiconductor device passivation SONY CORP 20 March 1975 [30 March 1974] 11691/75 Heading H1K The surface of a semiconductor substrate is passivated by a polycrystalline silicon layer containing from 2 to 45 atomic per cent oxygen. The layer may be applied to the PN junction of a rectifying diode but as described is applied to at least the guard ring protected collector junction of a diffused planar silicon transistor formed in an N type substrate or an N epitaxial layer on an N + substrate. In manufacture the oxide masking used in the diffusion steps is removed and the polycrystalline layer deposited from a mixture of silane and nitrous oxide in a flow of nitrogen with the substrate at 600- 750‹ C., and overcoated with vapour grown silicon dioxide optionally separated from the ploysilicon by a moisture resistant layer, e.g. of aluminium. If silicon tetrachloride is used instead of silane a temperature of 1100‹ C is necessary. Alternative sources of oxygen are NO 2 , NO, O 2 and H 2 O vapour. The oxygen is present as a mixture of silicon monoxide and dioxide at the grain boundaries but is also dispersed in the grains themselves, the dispersion being removed by annealing, e.g. at 1100‹C for 30 minutes. The mean grain size is preferably from 100-1000 Š, and all the grains preferably have sizes within this range. Although the collector breakdown voltage falls with increasing oxygen content the leakage current decreases and if the emitter junction is also covered the amplification factor increases but remains stable.

    24.
    发明专利
    未知

    公开(公告)号：DE69226687D1

    公开(公告)日：1998-09-24

    申请号：DE69226687

    申请日：1992-10-13

    Applicant: SONY CORP

    Inventor： OCHIAI AKIHIKO ,  HASHIMOTO MAKOTO ,  MATSUSHITA TAKESHI ,  YAMAGISHI MACHIO ,  SATO HIROSHI ,  SHIMANOE MUNEHARU

    IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8247 ,  H01L21/84 ,  H01L21/76

    Abstract: The present invention concerns a method of manufacturing a SOI substrate of forming a thin film of a silicon layer on an insulator substrate by bonding a substrate, wherein the method comprises successively: a step of forming an etching stopping layer on the surface of a silicon substrate, a step of forming an epitaxially grown silicon layer on said etching stopping layer, a step of bonding said silicon substrate formed with said silicon layer with another substrate as the insulator substrate, a step of grinding said silicon substrate from the rear face and etching it till said etching stopping layer is exposed and a step of removing said etching stopping layer.

    25.
    发明专利
    未知

    公开(公告)号：DE68920365T2

    公开(公告)日：1995-06-08

    申请号：DE68920365

    申请日：1989-06-16

    Applicant: MITSUBISHI MATERIAL SILICON ,  SONY CORP

    Inventor： SAITO YUICHI ,  SAKAI SHINSUKE ,  HAYASHI HISAO ,  MATSUSHITA TAKESHI

    IPC: B24B37/04 ,  H01L21/306 ,  B24B9/06

    Abstract: The present invention relates to a method for polishing a silicon wafer. The method comprises the steps of: (a) supplying a polishing fluid to a polishing surface, the polishing fluid including an alkaline fluid and polishing particles of high-purity silica dispersed in the alkaline fluid, the polishing surface being planar; (b) bringing a silicon wafer in contact with the polishing surface; and (c) moving at least one of the silicon wafer and the polishing surface relative to the other, thereby polishing the silicon wafer. The method is characterized by the following: the polishing surface is made of a ceramic material harder than the silicon wafer and more resistant to mechanochemical polishing than silicon, and the maximum roughness of the ceramic is less than 0.02 mu m.

    26.
    发明专利
    未知

    公开(公告)号：DE68922254D1

    公开(公告)日：1995-05-24

    申请号：DE68922254

    申请日：1989-08-23

    Applicant: SONY CORP

    Inventor： MATSUSHITA TAKESHI ,  SHIMANOE MUNEHARU ,  SATO HIROSHI ,  NIEDA AKIRA

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/82

    Abstract: A semiconductor memory having storage cells each comprising a MIS transistor (6, 7, 13) and a capacitor (1, 2, 10) comprises a semiconductor substrate (1), an insulating layer (3) formed on the semiconductor substrate (1), and semiconductor regions (5) formed on the surface of the insulating layer (3). The MIS transistors (6, 7, 13) are formed, respectively, on the surfaces of the semiconductor regions (5) and separated from each other and from the semiconductor substrate (1) by an insulating layer (3), and the capacitors (1, 2, 10) are formed, respectively, under the corresponding MIS transistors (6, 7, 13). A method of manufacturing the semiconductor memory includes a lapping process for lapping the surface of a wafer in forming the semiconductor regions (5) in recesses (4) formed in the insulating layer (3). The lapping process uses an alkaline liquid (156) as a lapping liquid and employs a lapping disc (155) provided with a hard lapping pad (154) to finish the surfaces of the semiconductor regions (5) flush with the surface of the insulating layer (3).

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