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    Semiconductor circuits
    1.
    发明授权
    Semiconductor circuits 失效
    半导体电路

    公开(公告)号：US3686684A

    公开(公告)日：1972-08-22

    申请号：US3686684D

    申请日：1970-05-26

    Applicant: SONY CORP

    Inventor： MATSUSHITA TAKESHI ,  YAGI HAJIME

    IPC: H01L29/00 ,  H01L31/111 ,  H01L11/00 ,  H01L9/12 ,  H01L15/00

    CPC classification number: H01L31/111 ,  H01L29/00

    Abstract: An electric circuit which exhibits negative impedance characteristics. Several embodiments are shown for producing ''''N'''' shape, ''''S'''' shape, and modified ''''N'''' shape negative impedance characteristics. The circuit includes a semiconductor device of the kind having three independent regions on a substrate, and a pair of bias sources; one source is applied between two of the regions, and the other is applied at least to the third region. By suitable bias arrangements the negative impedances are produced.

    Gate controlled rectifier
    2.
    发明授权
    Gate controlled rectifier 失效
    门控整流器

    公开(公告)号：US3914781A

    公开(公告)日：1975-10-21

    申请号：US48431174

    申请日：1974-06-28

    Applicant: SONY CORP

    Inventor： MATSUSHITA TAKESHI ,  HORINAGA HIROSHI ,  OHTSU TAKAJI ,  HAYASHI HISAO

    IPC: H01L29/10 ,  H01L29/744 ,  H01L29/74 ,  H01L29/06 ,  H01L29/90

    CPC classification number: H01L29/1016 ,  H01L29/744

    Abstract: A semiconductor PNPN large current switching device constructed such that the PN junction of the cathode N type region and a select portion of the P gating element located directly beneath the cathode contact lead is substantially nonconductive. In a preferred embodiment this is accomplished by highly doping the select portion of the P type gating region with an impurity to lower the electron injection efficiency of the adjacent portion of the cathode N type region. In another embodiment it is accomplished by constructing the select P type portion to have a greater thickness than the remaining portion of the gating P region, and in still another embodiment both of these features are employed.

    Abstract translation: 半导体PNPN大电流开关器件被构造成使得阴极N型区域的PN结和位于阴极接触引线正下方的P选通元件的选择部分基本上不导电。 在优选实施例中，这是通过用杂质高度掺杂P型选通区域的选择部分来实现的，以降低阴极N型区域的相邻部分的电子注入效率。 在另一个实施例中，通过将选择P型部分构造成具有比选通P区域的剩余部分更大的厚度来实现，并且在又一实施例中，采用了这两个特征。

    4.
    发明专利
    未知

    公开(公告)号：DE69328342D1

    公开(公告)日：2000-05-18

    申请号：DE69328342

    申请日：1993-12-09

    Applicant: SONY CORP

    Inventor： HAYASHI YUTAKA ,  MATSUSHITA TAKESHI

    IPC: G11C11/405 ,  G11C11/404 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/786 ,  G11C11/40

    Abstract: A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor (TR1) comprising a first semiconductor channel forming region (Ch1), first and second conductive regions (SC1, SC2) and a first conductive gate (G1); and a switching transistor (TR2) comprising a second semiconductor channel forming region (Ch2), third and fourth conductive regions (SC3, SC4) and a second conductive gate (G2); wherein said first conductive gate (G1) and said second conductive gate (G2) are connected to a first memory-cell-selection line (1ST LINE), said fourth conductive region (SC4) is connected to said first semiconductor channel forming region (Ch1), said third conductive region (SC3) is connected to a second memory-cell-selection line (2ND LINE), and said first conductive region (SC1) is connected to a read line (READ LINE).

    5.
    发明专利
    未知

    公开(公告)号：DE68922254T2

    公开(公告)日：1995-08-24

    申请号：DE68922254

    申请日：1989-08-23

    Applicant: SONY CORP

    Inventor： MATSUSHITA TAKESHI ,  SHIMANOE MUNEHARU ,  SATO HIROSHI ,  NIEDA AKIRA

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/82

    Abstract: A semiconductor memory having storage cells each comprising a MIS transistor (6, 7, 13) and a capacitor (1, 2, 10) comprises a semiconductor substrate (1), an insulating layer (3) formed on the semiconductor substrate (1), and semiconductor regions (5) formed on the surface of the insulating layer (3). The MIS transistors (6, 7, 13) are formed, respectively, on the surfaces of the semiconductor regions (5) and separated from each other and from the semiconductor substrate (1) by an insulating layer (3), and the capacitors (1, 2, 10) are formed, respectively, under the corresponding MIS transistors (6, 7, 13). A method of manufacturing the semiconductor memory includes a lapping process for lapping the surface of a wafer in forming the semiconductor regions (5) in recesses (4) formed in the insulating layer (3). The lapping process uses an alkaline liquid (156) as a lapping liquid and employs a lapping disc (155) provided with a hard lapping pad (154) to finish the surfaces of the semiconductor regions (5) flush with the surface of the insulating layer (3).

    6.
    发明专利
    未知

    公开(公告)号：DE3888885T2

    公开(公告)日：1994-11-03

    申请号：DE3888885

    申请日：1988-01-29

    Applicant: SONY CORP

    Inventor： HAYASHI HISAO ,  MATSUSHITA TAKESHI

    IPC: H01L27/00 ,  H01L21/02 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L21/90 ,  H01L23/52

    Abstract: On an n-type single-crystal silicon base (21), an insulating layer (22), a gate electrode (5), another insulating layer (2) and a middle layer (23) are formed using the CVD method. After polishing the top layer down to a flat surface (q), another insulating layer (44) and a silicon substrate (1) are formed, whichmakewhich makes a supporting body (11). The other side of the semiconductor layer (21) is then polished down (6), on top of which formed are o another insulating layer (24), another gate electrode (26), a soruce region (27), a drain region (28), another insulating layer (29), a source electrode (31) and a drain electrode (32). These electrodes (31,32) form a part of a second layer (6) as opposed to a first wiring layer (5) consisting of the gate electrode.

    CMOS TYPE STATIC RANDOM ACCESS MEMORIES
    7.
    发明专利
    CMOS TYPE STATIC RANDOM ACCESS MEMORIES 未知

    公开(公告)号：GB2254487A

    公开(公告)日：1992-10-07

    申请号：GB9206123

    申请日：1992-03-20

    Applicant: SONY CORP

    Inventor： HASHIMOTO MAKOTO ,  MIYAZAWA YOSHIHIRO ,  MATSUSHITA TAKESHI

    IPC: H01L27/11

    Abstract: A method of manufacturing a CMOS type SRAM, comprises the steps of forming a first mask layer 13 on a semiconductor layer 11, and patterning the layer 13 to define semiconductor islands A, B where a driver MOS transistor and a load MOS transistor are formable with an isolation region 18 therebetween; forming a second mask layer 15 and patterning it to overlap the region in which one of the transistors is to be formed; but not to overlap the isolating region between the transistors; masking, with a resist film 17, the region in which the other of the transistors is to be formed; and etching the layer 13 while it is masked by the resist film 17 and the layer 15; and etching the semiconductor layer 11 while it is masked by the layer 13, thereby forming mutually isolated semiconductor islands A and B where the transistors are formed.

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