公开(公告)号：JP2000075158A

公开(公告)日：2000-03-14

申请号：JP24594298

申请日：1998-08-31

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OGAWA TAKESHI

IPC: G02B6/122 ,  G02B6/13

Abstract: PROBLEM TO BE SOLVED: To obtain a process for producing an optical waveguide which forms clad layers and core layers of a uniform thickness on a substrate. SOLUTION: This process for producing the optical waveguide has a first spin coating stage for forming a lower clad layer precursor 5 thin film on the substrate 1, a stage for forming the lower clad layer 2 by curing the same, a second spin coating stage for forming a core layer precursor thin film on the lower clad layer 2, stage for forming the core layer by curing the same, a stage for forming a core layer by patterning the lower clad layer 2, a third spin coating stage for forming an upper clad layer precursor thin film covering the lower clad layer 2 and the core part and a stage for forming an upper clad layer by curing the same. All of the first, second and third spin coating stages have the stage for using substrate holders 6 having a recessed part 6a of the diameter slightly larger than the outside diameter of the substrate 1 and nearly the same depth as the thickness of the substrate 1, i.e., the recessed part 6a which is the female mold of the substrate 1.

Abstract translation: 要解决的问题：获得在基板上形成均匀厚度的覆层和芯层的光波导的制造方法。 解决方案：该光波导的制造方法具有：在基板1上形成下包层前体5的薄膜的第一旋涂阶段，通过固化下层包层2的阶段，第二旋涂阶段， 在下包层2上形成芯层前体薄膜，通过使其固化来形成芯层的阶段，通过图案化下包层2形成芯层的阶段，用于形成上包层的第三旋涂阶段 覆盖下包层2和芯部的层前体薄膜，以及通过使其固化来形成上覆层的阶段。 所有第一，第二和第三旋涂阶段都具有使用具有比基板1的外径稍大的直径略大于基板1的厚度的深度的凹部6a的基板保持件6的阶段， 即作为基板1的阴模的凹部6a。

公开(公告)号：JP2000047044A

公开(公告)日：2000-02-18

申请号：JP21785698

申请日：1998-07-31

Applicant: SONY CORP

Inventor： OGAWA TAKESHI

IPC: G02B6/122 ,  H04B10/11 ,  H04B10/40 ,  H04B10/50 ,  H04B10/60 ,  H04B10/80 ,  H04B10/02 ,  H04B10/10 ,  H04B10/105 ,  H04B10/22 ,  H04B10/28

Abstract: PROBLEM TO BE SOLVED: To precisely form a reflection surface for bending an optical path on an incident stage and an emission stage of an optical waveguide by a method suitable for mass production. SOLUTION: A mirror layer 4 is formed using material of etching selectivity or developer solubility different from those of a core 3 and a clad 2 constituting the optical waveguide. For forming this mirror layer 4, a lower part clad layer being the lower half of the clad layer 2 is formed, and the core 3 is patterned on it, and a mirror forming layer formed by coating the whole of a substrate is etched just under an etching mask so as to be undercut, or is patterned through photolithography and development processing. Even by either method, a tilted angle θ of an incident side reflection surface 5 and an emission side reflection surface 6 is decided self-consistently. A half mirror characteristic is added to both reflection surfaces, and the mirror layer 4 itself may be used as the core of the optical waveguide also.

公开(公告)号：JPH09267474A

公开(公告)日：1997-10-14

申请号：JP10336096

申请日：1996-03-31

Applicant: SONY CORP

Inventor： OGAWA TAKESHI

IPC: B41J2/045 ,  B41J2/055 ,  B41J2/205 ,  H04N1/034 ,  H04N1/23

Abstract: PROBLEM TO BE SOLVED: To stably prepare a beautiful photoprint by generating a driving signal based on frequency characteristics of a response displacement to the driving signal of one wall surface of a liquid chamber to control a pressurizing means in an apparatus which discharges a liquid from the liquid chamber via a nozzle by pressurizing one wall surface of the liquid chamber. SOLUTION: In printing, a signal processing control circuit 31 calculates a response displacement waveform of a diaphragm of a printing head 1 based on an input signal S10, and converts that into a frequency domain by Fourier conversion. By dividing the converted response displacement waveform by frequency responce characteristics of response displacement of the diaphragm to a driving signal 11, a frequency component of a pulse waveform of the driving signal S11 is calculated. Then, by reverse Fourier conversion of a pulse waveform of the frequency component, it is converted to a time domain to obtain the pulse form for obtaining response displacement waveform. By impressing the pulse form to the electrode via a driver 32 as the driving signal S11, printing is carried out by driving each sinking comb part of a laminated piezoelectric element.

公开(公告)号：JPH0822042A

公开(公告)日：1996-01-23

申请号：JP18074294

申请日：1994-07-08

Applicant: SONY CORP

Inventor： KIJIMA KOUICHIROU ,  OGAWA TAKESHI ,  WATARI AKIE

IPC: G02B6/13 ,  G02B6/12 ,  G02F1/37

Abstract: PURPOSE:To provide an optical waveguide device and the production of an optical waveguide device and an optical waveguide by which the power density of light in the optical waveguide can be increased and a process of accurate positioning can be eliminated. CONSTITUTION:In this optical waveguide device, a protective film 2 essentially comprising SiO2 (silicon dioxide) and Ta2O5 (tantalum pentoxide) is formed as a mask material on an optical waveguide material layer of a substrate 1 comprising LiNbxTa(1-x)O3 (0

公开(公告)号：JP2009043962A

公开(公告)日：2009-02-26

申请号：JP2007207617

申请日：2007-08-09

Applicant: Sony Corp ,  ソニー株式会社

Inventor： MIYAZAKI HIROHITO ,  OGAWA TAKESHI ,  NAKAYAMA HIROKAZU ,  TAKESHIMA NAMIKO

IPC: H01L27/00 ,  H01L21/02 ,  H01L23/12

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor apparatus which is manufactured simply and inexpensively. SOLUTION: Firstly, a stripping layer 110 which can absorb ultraviolet light is formed on a support substrate 100 transparent to the ultraviolet light, and, thereafter, an adhesive layer 130 which can absorb ultraviolet light, and chips 11 and 12 are laminated in this order from a stripping layer 110 on a predetermined region of a surface of the stripping layer 110. For the stripping layer 110, a material is used whose light volume per unit area for hardening by ultraviolet light irradiation is a first light volume, and, for the adhesive layer 130, a material is used whose light volume per unit area for hardening by ultraviolet light irradiation is a second light volume smaller than the first light volume. Thereafter, ultraviolet light L1 having a light volume per unit area less than the first light volume and larger than the second light volume is irradiated to the adhesive layer 130 through the support wafer 100 and the stripping layer 110 from a support wafer 100 side. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 解决的问题：提供一种制造简单廉价的半导体装置的制造方法。 解决方案：首先，在对紫外线透明的支撑基板100上形成能够吸收紫外线的剥离层110，然后，将能够吸收紫外线的粘合层130和芯片11,12层合 从汽提层110的表面的预定区域上的剥离层110按顺序排列。对于剥离层110，使用通过紫外线照射进行硬化的单位面积的光量为第一光量的材料， 对于粘合剂层130，使用通过紫外线照射进行硬化的单位面积的光量为比第一光体积小的第二光体积的材料。 此后，通过支撑晶片100和剥离层110从支撑晶片100侧将粘合剂层130照射到具有小于第一光体积并且大于第二光体积的单位面积的光体积的紫外线L1。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2006245057A

公开(公告)日：2006-09-14

申请号：JP2005054842

申请日：2005-02-28

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OGAWA TAKESHI ,  NAKAYAMA HIROKAZU

IPC: H01L25/18 ,  G02B6/122 ,  H01L23/14 ,  H01L25/04 ,  H01L25/16 ,  H01L31/0232 ,  H01L33/48

CPC classification number: G02B6/12002 ,  G02B6/12004 ,  G02B6/4214 ,  G02B2006/12173 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/167 ,  H01L31/0203 ,  H01L31/12 ,  H01L2224/24227 ,  H01L2224/82039 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15157 ,  H01L2924/15165 ,  H01L2924/30105 ,  H01L2924/351 ,  H05K1/0274 ,  H05K1/185 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/48 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To improve packaging precision and packaging efficiency of packaging components, and to attain thin structure and densification. SOLUTION: A hybrid module includes a silicon substrate 3 in which a plurality of components loading recesses 7 are formed, a plurality of sorts of packaging components 4 in which it is loaded into each components loading recess 7 and which are fixed by an adhesion resin layer 8, and a wiring layer 5 formed on the silicon substrate 3. Each packaging component 4 makes opposing outside face input/output section formation side 9, a components loading recess 7 is loaded with them, it is mounted in the state that the adhesion resin layer 8 is fixed in its periphery, and it is laid under the silicon substrate 3. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提高包装部件的包装精度和包装效率，并实现薄型结构和致密化。 解决方案：混合模块包括其中形成有多个部件装载凹部7的硅基板3，多个包装部件4，其中装载到每个部件装载凹部7中并且由一个 粘合树脂层8和形成在硅基板3上的布线层5.每个包装部件4制成相对的外表面输入/输出部分形成侧9，部件装载凹部7装载它们， 附着树脂层8固定在其周边，并且被放置在硅衬底3的下面。（C）2006年，JPO＆NCIPI

公开(公告)号：JP2004146603A

公开(公告)日：2004-05-20

申请号：JP2002309978

申请日：2002-10-24

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OGAWA TAKESHI

IPC: G02B6/122 ,  H01L23/02 ,  H01L25/16 ,  H01L31/12

CPC classification number: G02B6/43 ,  G02B6/4214 ,  H01L24/97 ,  H01L25/167 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/00 ,  H01L2224/05599

Abstract: PROBLEM TO BE SOLVED: To reduce parasitic capacitance in a compound module of an electric chip and an optical chip. SOLUTION: When a semiconductor chip 5 mounted on the first major surface 7a of a resin layer 7 is connected with an optical chip 6 buried in the second major surface 7b of the resin layer 7 through interlayer vias 10, the semiconductor chip 5 and the optical chip 6 can be connected through a shortest distance and thereby parasitic capacitance incident to connection of the semiconductor chip 5 and the optical chip 6 can be reduced. Furthermore, production yield can be enhanced while reducing the size. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：减少电子芯片和光学芯片的复合模块中的寄生电容。 解决方案：当安装在树脂层7的第一主表面7a上的半导体芯片5通过层间通孔10与埋在树脂层7的第二主表面7b中的光学芯片6连接时，半导体芯片5 并且可以通过最短距离连接光学芯片6，从而可以减少入射到半导体芯片5和光学芯片6的连接的寄生电容。 此外，可以在减小尺寸的同时提高产量。 版权所有（C）2004，JPO

公开(公告)号：JP2004039867A

公开(公告)日：2004-02-05

申请号：JP2002195018

申请日：2002-07-03

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OGAWA TAKESHI

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/538 ,  H01L25/04 ,  H01L25/18 ,  H05K3/00 ,  H05K3/20 ,  H05K3/28 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01L23/3121 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/0023 ,  H05K3/0058 ,  H05K3/205 ,  H05K3/284 ,  H05K3/423 ,  H05K3/465 ,  H05K3/4682 ,  H05K2203/025 ,  H05K2203/0733

Abstract: PROBLEM TO BE SOLVED: To miniaturize and fine a viahole and a wiring pattern and thin the whole.
SOLUTION: Photo lithography treatment is performed to a first insulating layer 22 wherein the respective unit wiring layers 8-12 are formed of photosensitive insulating resin material, and a viahole trench 25 is formed. Photo lithography treatment is performed to a second insulating layer 23 which is formed on the first insulating layer 22 by using photosensitive insulating resin material, and a wiring trench 27 is formed. A conductor metal layer 24 is so formed on the second insulating layer 23 that the viahole trench 25 and the wiring trench 27 are filled with conductor metal. Polishing treatment is performed to the conductor metal layer 24 until a main surface of the second insulating layer 23 is exposed, and a viahole 13 and a wiring pattern 26 are formed by using the conductor metal with which the insides of the viahole trench 25 and the wiring trench 27 are filled.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002368428A

公开(公告)日：2002-12-20

申请号：JP2001176350

申请日：2001-06-11

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OGAWA TAKESHI ,  OKUHORA AKIHIKO ,  NAKAYAMA HIROKAZU

IPC: H05K3/46 ,  H01L23/12

CPC classification number: H01L23/552 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/3025

Abstract: PROBLEM TO BE SOLVED: To reduce in size and cost of a package by thinning the package with a high accuracy and a high function. SOLUTION: A board unit for a high-frequency module comprises a base board 2 formed by flattening an uppermost layer by multilayer wiring on an organic base board 5 to a build-up forming surface 3, and a high-frequency circuit 4 formed with multilayer wiring layers 32 and 34 having passive elements via insulating layers 31 and 33 according to a thin film technique and a thick film technique on the build-up forming surface 3. An inductor element 37 for a high frequency is formed in an inner layer side wiring layer 31 of the circuit 4, and an inductor element 338 for a low frequency is formed in the front layer side wiring layer 34 formed thicker than the inner layer side wiring layer 31.

Abstract translation: 要解决的问题：通过以高精度和高功能使包装变薄来减小包装的尺寸和成本。 解决方案：用于高频模块的电路板单元包括通过有机基板5上的多层布线将最上层平坦化到堆积形成表面3而形成的基板2和形成有多层的高频电路4 根据薄膜技术和厚膜技术，在积层形成表面3上经由绝缘层31和33具有无源元件的布线层32和34.高频的电感器元件37形成在内层侧布线 在内层侧布线层31形成的前层侧布线层34上形成电路4的层31和低频用电感器元件338。

公开(公告)号：JP2002033583A

公开(公告)日：2002-01-31

申请号：JP2000218199

申请日：2000-07-19

Applicant: SONY CORP

Inventor： OGAWA TAKESHI

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a formation method for an insulating layer and a via (a connecting hole), wherein the surface of the formed insulating layer becomes smooth, a thin-film element or the like can be formed with good reliability at good yield and with a high degree of freedom, and a very small via can be formed when the insulating layer and the via are formed, to provide a multilayer wiring board which uses the formation method, to provide a wiring structure for a module board or the like and to provide its formation method. SOLUTION: A mask substrate 21 is arranged through a pedestal 20. A photosensitive insulating material 3A such as a photosensitive epoxy resin or the like is interposed between the substrate 21 and a core substrate 1 it is pattern- exposed and developed, and a via hole 7 is formed. By its developing, the very small via hole 7 can be formed. The surface of a, insulating material (consequently, the insulating layer 3) can be made flat and smooth by a face 21a facing the mask substrate 21, and the insulating layer can be always formed in a set thickness.