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    22.
    发明专利
    未知

    公开(公告)号：DE69219934D1

    公开(公告)日：1997-07-03

    申请号：DE69219934

    申请日：1992-03-26

    Applicant: SONY CORP

    Inventor： SAKAMOTO ETSUROU

    IPC: H03F1/32 ,  H03G3/30 ,  H04B1/62 ,  H04N5/923 ,  H04N5/92

    Abstract: A compensating deemphasis circuit (50) is connected to a preemphasis circuit (10A) in series. The deemphasis circuit (50) has the same characteristic as a deemphasis circuit (20B) provided in a playback system. An input signal and an output signal which are connected in series are supplied to a subtracter (41). The subtracter extracts a distortion component. This distortion component is overlapped (43) to an output signal of the preemphasis circuit (10A) through a weight coefficient generating device (42). When the signal passes through the deemphasis circuit in the record and playback system and that in the playback system, the distortion component is canceled.

    23.
    发明专利
    未知

    公开(公告)号：DE69119846T2

    公开(公告)日：1996-12-12

    申请号：DE69119846

    申请日：1991-08-23

    Applicant: SONY CORP

    Inventor： SAKAMOTO ETSUROU

    IPC: H04N9/80 ,  H04N9/79 ,  H04N9/81 ,  H04N9/82 ,  H04N9/896

    Abstract: In video signal recording apparatus a video signal is processed (3, 5, 6, 10, 11), such as in time division multiplexed format. A burst clock signal (B) of frequency fb is generated (8) for recovering the video signal during a subsequent reproduction operation, and this burst clock signal (B) is added (40A, 40B) to a DC level portion (H) that is present in the processed video signal, resulting in a combined signal. The combined signal is frequency modulated (14A, 14B) and recorded ( 70 ) on a record medium ( 18 ). Assuming that the DC level (H) of the processed video signal is represented by a modulating frequency fa, and m is an integer, if:

    24.
    发明专利
    未知

    公开(公告)号：DE69120633T2

    公开(公告)日：1996-11-28

    申请号：DE69120633

    申请日：1991-11-14

    Applicant: SONY CORP

    Inventor： SAKAMOTO ETSUROU ,  TAKASHIMA MASATOSHI

    IPC: H04N5/7826 ,  H04N5/928 ,  H04N7/015 ,  H04N9/793 ,  H04N9/797 ,  H04N9/81 ,  H04N9/815 ,  H04N9/79

    Abstract: A video signal processing apparatus, typically for use as a video tape recorder/recording for recording and reproducing high-definition television signals, includes an encoder (4) for converting a chrominance signal (PR, PB) into a line sequential signal and multiplexing the line sequential signal with a luminance signal (Y) on time compression according to time-division multiplexing, thereby producing a time-division-multiplexed signal. A vertical emphasis circuit (31R, 31B) is connected to an input terminal of the encoder (4), for effecting vertical nonlinear emphasis on the chrominance signal (PR, PB). The video signal processing apparatus also includes a vertical low-pass filter (32R, 32B) for removing aliasing distortions from the chrominance signal (PR, PB) into the line sequential signal. The vertical nonlinear emphasis is effected on the chrominance signal (PR, PB) after the chrominance signal (PR, PB) has been processed by the vertical low-pass filter (32R, 32B).

    25.
    发明专利
    未知

    公开(公告)号：DE69120633D1

    公开(公告)日：1996-08-08

    申请号：DE69120633

    申请日：1991-11-14

    Applicant: SONY CORP

    Inventor： SAKAMOTO ETSUROU ,  TAKASHIMA MASATOSHI

    IPC: H04N5/7826 ,  H04N5/928 ,  H04N7/015 ,  H04N9/793 ,  H04N9/797 ,  H04N9/81 ,  H04N9/815 ,  H04N9/79

    Abstract: A video signal processing apparatus, typically for use as a video tape recorder/recording for recording and reproducing high-definition television signals, includes an encoder (4) for converting a chrominance signal (PR, PB) into a line sequential signal and multiplexing the line sequential signal with a luminance signal (Y) on time compression according to time-division multiplexing, thereby producing a time-division-multiplexed signal. A vertical emphasis circuit (31R, 31B) is connected to an input terminal of the encoder (4), for effecting vertical nonlinear emphasis on the chrominance signal (PR, PB). The video signal processing apparatus also includes a vertical low-pass filter (32R, 32B) for removing aliasing distortions from the chrominance signal (PR, PB) into the line sequential signal. The vertical nonlinear emphasis is effected on the chrominance signal (PR, PB) after the chrominance signal (PR, PB) has been processed by the vertical low-pass filter (32R, 32B).

    28.
    发明专利
    未知

    公开(公告)号：DE69110491T2

    公开(公告)日：1995-11-09

    申请号：DE69110491

    申请日：1991-02-14

    Applicant: SONY CORP

    Inventor： SAKAMOTO ETSUROU

    IPC: H04N5/922 ,  G11B20/06 ,  H03C3/00 ,  H03D3/04 ,  H04N5/931 ,  H04N9/79

    Abstract: The demodulating apparatus (10) suitable for use in a VTR or the like. It has a suppressing circuit (20) for suppressing sideband components of FM modulated waves, a pulse counter type demodulation circuit (30) for demodulating the output from the suppressing circuit (20) and a recovering circuit (40) connected to the output of the FM demodulation circuit (30) for recovering the sideband components suppressed by the suppressing circuit (20), to thereby provide a favorable demodulation. The suppressing (20) and recovering (40) circuits advantageously comprise a sine and a cosine equalizer. The suppression of the sideband components results in lowering the modulation figure thereby reducing fluctuations in amplitude and distortion. Recovering the suppressed sidebands prevents drop-out of information.

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