公开(公告)号：JPS5646558A

公开(公告)日：1981-04-27

申请号：JP12304879

申请日：1979-09-25

Applicant: SONY CORP

Inventor： OOTSU KOUJI ,  SHIMADA TAKASHI

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/43 ,  H01L29/78

Abstract: PURPOSE:To contrive the improvement in the performance of a semiconductor device and the increase in the density thereof by forming the gate electrode of a complementary insulated gate FET of an N type polysilicon and also forming most electrode wirings except a part of the polysilicon. CONSTITUTION:A P type layer 2 is formed on an N type Si substrate 1, N type layers 3, 4 are formed in the layer 2, and P type layers 9, 10 are formed in the substrate 1. A gate oxide film 5 and a field oxide film 16 are covered with an N type polysilicon 25. Subsequently, a BSG26 is formed on the layers 9, 10, a B is diffused therein, and the polysilicon 25 directly thereunder is transformed into a P type layer 27. Then, aluminum 28 is evaporated thereon, is selectively etched, and there are formed on the respective gate films 5 gate electrodes 29, 30, source electrodes 31, 32 with N type polysilicon and wire 33 for connecting the layer 4 to the layer 10. When P type and N type polysilicons 25, 27 having different etching speeds are plasma etched together with the aluminum 28, they can be etched in the same width. Eventually, an SiO2 film 34 is covered thereon, and it is completed. According to this configuration the C-MOS can be provided with stable gate, its wiring resistance can be lowered, and there can be obtained a complmentary semiconductor device which has high performance and high integrity.

公开(公告)号：JPS54104233A

公开(公告)日：1979-08-16

申请号：JP1075878

申请日：1978-02-02

Applicant: SONY CORP

Inventor： MATSUMOTO HIROYUKI ,  SHIMADA TAKASHI ,  YAMAZAKI HIROSHI

IPC: H01L27/148 ,  H01L31/00 ,  H04N5/30 ,  H04N5/335 ,  H04N5/341 ,  H04N5/361 ,  H04N5/3728

Abstract: PURPOSE:To simplify a process of manufacture with a dark current reduced by evading from providing a channel stopper region between vertical and horizontal shift registers in a buried-channel type solid pickup device. CONSTITUTION:On one main surface of P-type semiconductor substrate 20 of low impurity density, active region 7 is formed which is composed of part 7S constituting each photo detection part 3, part 7R constituting vertical shift register 4 extending to each photo detection part, etc. Among active regions 7, only basic region 8 resides, and the surface potential of region 8 is lower than the lowest potential of minimum potentials of regions 7. Onto the main surface of substrate 20, insulation layer 8, storage gate electrode 9, 2nd insulation layer 10, transfer gate electrode 11, 3rd insulation layer 13, and sensor electrode 14 are adhered respectively.

公开(公告)号：JPS54102883A

公开(公告)日：1979-08-13

申请号：JP914078

申请日：1978-01-30

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI ,  YAMAGUCHI JIROU

IPC: H01L29/78 ,  H01L21/768 ,  H01L23/522

Abstract: PURPOSE:To reduce the size, by forming MOSFET with self alignment and making self alignement FET and wiring region mutually. CONSTITUTION:The SiO2 film 24 on the N Si substrate 21 is selectively opened 22,23, it is covered with the SiO2 film 25 added with B and the film 25 is selectively opened for window. After making the surface thermal oxidation film 26 and the P diffusion layers 27 and 28, the film 26 is opened 29 and it is covered with the B added poly Si 30. The layer 30 is selectively removed, the film 26 is removed by taking the gate electrode 51 as a mask, and the P layers 31 and 32 are diffused. Further, it is covered with CVDSiO2 film 33 and the Al wiring 35 and the layer 52 are formed with selective opening. Thus, the wiring P layer 27 is possible for cubic crossing for three layers of Al wiring and the overall area occupied by wiring can be reduced.

公开(公告)号：JPS54101680A

公开(公告)日：1979-08-10

申请号：JP844878

申请日：1978-01-27

Applicant: SONY CORP

Inventor： MOCHIZUKI HIDENOBU ,  SHIMADA TAKASHI ,  OOTSU KOUJI ,  HIRATA YOSHIMI ,  YAMAGUCHI JIROU

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092

Abstract: PURPOSE:To reduce a threshold voltage by forming respective gate electrodes of P(N) channel MOS transistors by P(N)-type impurity-doped poly-crystal Si layers. CONSTITUTION:The gate electrode of a N channel MOS transistor, namely, poly- crystal Si layer 11 is formed with N-type impurity-doped poly-crystal Si, and the other P channel MOS transistor is formed similarly. Both poly-crystal Si layers 11 and 12 are extended near channel stopper region 10. In this constitution, since respective gates are constituted by impurity-doped poly-crystal Si layers 11 and 12, the threshold voltage can be reduced. Meanwhile, this constitution is advantageous to improve an integration degree because electrodes 14S, 14D 15S and 15D which are taken out from souce and drain regions are formed by conductive poly-crystal Si layers.

公开(公告)号：JPS5357771A

公开(公告)日：1978-05-25

申请号：JP13258176

申请日：1976-11-04

Applicant: SONY CORP

Inventor： MOCHIZUKI HIDENOBU ,  OOTSU KOUJI ,  SHIMADA TAKASHI

IPC: H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:A non-volatile memory transistor of high reliability is obtained by increasing the change amount V th of a threshold voltage V th thereby prolonging the holding time of memory and simultaneously increasing the dielectric strength of a gate insulation layer.

公开(公告)号：JPS5119972A

公开(公告)日：1976-02-17

申请号：JP9184074

申请日：1974-08-10

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI ,  SAIKI SHINICHI ,  KASHINUMA AKIO

IPC: H01L29/73 ,  H01L21/283 ,  H01L21/31 ,  H01L21/331 ,  H01L29/70

公开(公告)号：JPH07297303A

公开(公告)日：1995-11-10

申请号：JP11034594

申请日：1994-04-26

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To enable low-voltage operation, prevent the degree of integration from being lowered, and increase the yield. CONSTITUTION:On an SiO2 film 12 in which an element insulation region is formed, a polycrystalline Si film 15 as a floating gate has a protruded part 15a including a component perpendicular to the direction in which a polycrystalline Si film 17 as a control gate extends. Therefore, the ratio of the coupling capacitance between the floating gate and a channel region to the coupling capacitance between the control gate and the floating gate is small. In addition, since contact holes 21, 22 and 24 are provided between the control gates which extend in parallel to one another, the memory cell area is not increased by the protruded part 15a.

公开(公告)号：JPH0472664A

公开(公告)日：1992-03-06

申请号：JP18404290

申请日：1990-07-13

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L27/148 ,  H04N5/335 ,  H04N5/369 ,  H04N5/372

Abstract: PURPOSE:To photoelectrically convert light selectively without forming a filter by a method wherein impurity diffusion regions having different depths are formed in such a way that incident light having different wavelength regions in a photodetection part 2 is photoelectrically converted selectively. CONSTITUTION:A photodetection part 2 is formed so as to be surrounded by a p-type well region 5. It is provided with the following: an n type impurity diffusion region 11 for photoelectric conversion use; and a p type impurity diffusion region 11 for light-absorption and recombination use. The depth of the p type impurity diffusion region 12 from the surface of a substrate is designated as LP2, and the depth of the n type impurity diffusion region 11 is designated as XN2. In this case, LP2 type impurity diffusion region 11 is situated in the lower part of the p type impurity diffusion region 12. Since the photodetection part 2 is formed of the impurity diffusion regions whose depths are different as described above, it is possible to read out a color image signal without forming a color filter.

公开(公告)号：JPH0319330A

公开(公告)日：1991-01-28

申请号：JP15225389

申请日：1989-06-16

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI ,  KIYOTA HISAHARU

IPC: H01L21/3205 ,  H01L21/28

Abstract: PURPOSE:To make a contact hole in the least contact resistance value at no increase in the leakage current in the inverse direction even after the heat treatment process by a method wherein the second diffused layer having a deeper junction part is formed in the first diffused layer region having a shallow junction part; a silicide layer having narrower region than the said region is formed therein; an interlayer insulating film is formed on the whole surface; a contact hole is made in the silicide layer; and a high melting point metal is embedded in the contact hole. CONSTITUTION:The first p-type diffused layer 1 having a shallow junction part is formed on a substrate 8. The second p type diffused layer 2 is formed in the first opening part 7. The second diffused layer 2 having a deeper junction part than that of the first diffused layer is formed in the first diffused layer region. Next, a silicide layer 11 is formed in the second diffused layer 2 part exposed to the bottom of the second opening part 8. Finally, the second insulating film 6 and the sidewall 8 thereof both comprising SiO2 are etched away; a new interlayer insulating film 12 comprising, e.g. SiO2 is formed on the whole surface; a contact hole 13 is made in the silicide layer 11; and a high melting point metal 14 is embedded in the contact hole 13 so as to a multilayer wiring.

公开(公告)号：JPH02275634A

公开(公告)日：1990-11-09

申请号：JP9705889

申请日：1989-04-17

Applicant: SONY CORP

Inventor： SHIMADA TAKASHI

IPC: H01L21/76 ,  H01L21/3205

Abstract: PURPOSE:To form a flattened film having no stepped section by the recessed section and projecting section of the surface of a base body without using a mask by successively repeating the bias-application deposition of a film onto the base body and the etchback of the deposited film plural times. CONSTITUTION:The recessed section 14 of the surface of a base body 11 is buried with a film 15 through bias-application deposition, the film 15 is deposited even onto the polycrystalline Si/SiO2 film 12 of the projecting section of the surface of the base body 11, and an inclined section 15a is shaped at the end section of the film 15. Since the etching rate of the inclined section 15a is made faster than that of a flat section 15b in subsequent etchback, the speed of the etchback of the film 15 deposited onto the projecting section is made larger than that of the film 15 burying the recessed section 14. Consequently, when bias-application deposition and etchback are repeated successively plural times, the stepped section of the recessed section 14 and projecting section of the surface of the base body 11 can be removed. Accordingly, the flattened film 15 can be formed without using a mask.