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公开(公告)号：DE69320403T2
公开(公告)日：1998-12-24
申请号：DE69320403
申请日：1993-05-21
Applicant: SONY CORP
Inventor： SHIMPUKU YOSHIHIDE , INO HIROYUKI , CHAKI YASUYUKI , NAKAGAWA TOSHIYUKI
IPC: G11B7/00 , G11B7/004 , G11B7/0045 , G11B20/14
Abstract: A method of modulating digital data to a variable-length code (d, k; m, n; r) for recording information on and reproducing the same from an optical disc (21). The optimal range of a minimum run length d corresponding to the minimum number of successive same symbols is determined by a procedure which comprises a first step (52, 53) to determine the minimum S/N required for obtaining a desired error rate from the relationship between a bit error rate and the S/N when d = 0; a second step (54) to obtain the relationship between a change of the numerical value d and that of the S/N by calculating, on the basis of the required minimum S/N obtained at the first step (52, 53), the S/N loss caused due to the change of the numerical value d; and a third step (55) to determine, from the relationship between the numerical value d and the S/N, the range of the value d corresponding to the S/N of the transmission characteristic dependent on an optical system and an optical disc (21).
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公开(公告)号：ES2119833T3
公开(公告)日：1998-10-16
申请号：ES93108290
申请日：1993-05-21
Applicant: SONY CORP
Inventor： SHIMPUKU YOSHIHIDE , INO HIROYUKI , CHAKI YASUYUKI , NAKAGAWA TOSHIYUKI
IPC: G11B7/004 , G11B7/00 , G11B7/0045 , G11B20/14
Abstract: A method of modulating digital data to a variable-length code (d, k; m, n; r) for recording information on and reproducing the same from an optical disc (21). The optimal range of a minimum run length d corresponding to the minimum number of successive same symbols is determined by a procedure which comprises a first step (52, 53) to determine the minimum S/N required for obtaining a desired error rate from the relationship between a bit error rate and the S/N when d = 0; a second step (54) to obtain the relationship between a change of the numerical value d and that of the S/N by calculating, on the basis of the required minimum S/N obtained at the first step (52, 53), the S/N loss caused due to the change of the numerical value d; and a third step (55) to determine, from the relationship between the numerical value d and the S/N, the range of the value d corresponding to the S/N of the transmission characteristic dependent on an optical system and an optical disc (21).
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公开(公告)号：DE69320721D1
公开(公告)日：1998-10-08
申请号：DE69320721
申请日：1993-06-29
Applicant: SONY CORP
Inventor： SHIMPUKU YOSHIHIDE , INO HIROYUKI , CHAKI YASUYUKI , NAKAGAWA TOSHIYUKI
Abstract: A synchronization detector includes a NRZI circuit (2) for extracting edge portions of RF signals detected as binary-valued signals to form a pulse train, a counter (6) for counting the number of channel clocks in the distance between transitions represented by the edge portions, a latch circuit (5) operated responsive to pulses from the NRZI circuit for holding a number of previously counted channel clocks immediately preceding a current count of channel clocks, and AND gates (7, 8, 9, 10, 11, 12) and an OR gate (13) for detecting synchronization signals when the combination of the channel clocks from the counter and the latch circuit is the combination of the maximum distance between transitions Tmax and Tmax-kT (k = 1 or 2) of a (d, k; m, n; r) modulation code. Synchronization signals may be detected promptly even if the frame structure is increased in size to enable restoration of synchronization to be expedited when frame structure synchronization is not in order. A demodulator utilizing the synchronization signal detector is also disclosed.
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公开(公告)号：CA2096792A1
公开(公告)日：1993-11-26
申请号：CA2096792
申请日：1993-05-21
Applicant: SONY CORP
Inventor： SHIMPUKU YOSHIHIDE , INO HIROYUKI , CHAKI YASUYUKI , NAKAGAWA TOSHIYUKI
Abstract: A method of modulating digital data to a variable-length code (d, k; m, n; r) for recording information on and reproducing the same from an optical disc. The optimal range of a minimum run length d corresponding to the minimum number of successive same symbols is determined by a procedure which comprises a first step to determine the minimum S/N required for obtaining a desired error rate from the relationship between a bit error rate and the S/N when d = 0; a second step to obtain the relationship between a change of the numerical value d and that of the S/N by calculating, on the basis of the required minimum S/N obtained at the first step, the S/N loss caused due to the change of the numerical value d; and a third step to determine, from the relationship between the numerical value d and the S/N, the range of the value d corresponding to the S/N of the transmission characteristic dependent on an optical system and an optical disc.
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25.发明专利
公开(公告)号：CA2091208A1
公开(公告)日：1993-09-11
申请号：CA2091208
申请日：1993-03-08
Applicant: SONY CORP
Inventor： INO HIROYUKI , SHIMPUKU YOSHIHIDE , CHAKI YASUYUKI , NAKAGAWA TOSHIYUKI
Abstract: A modulating method and apparatus and a demodulating method and apparatus in which a variable length code (d, k;m, n,r) which can provide a greater minimum reversal distance to allow recording of a higher density than ever is provided. According to the modulating method and apparatus, digital data of a basic data length of m bits is modulated into a variable length code (d, k;m, n;r) of a basic code length of n bits, and where the distance between adjacent ones of the digital data is represented by T, the minimum reversal distance of the variable length code is equal to or greater than 2.0T and the minimum length of a run of a same symbol is equal to or greater than 4. The demodulating apparatus demodulates the digital data back into the variable length code and comprises storage means for storing therein a plurality of tables for converting the digital data into the variable length code, discriminating means for discriminating the binding length of the digital data, and selecting means for selecting one of the tables in accordance with a result of discrimination of the discriminating means.
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Patent Agency Ranking26.发明专利
公开(公告)号：ZA200000371B
公开(公告)日：2001-03-02
申请号：ZA200000371
申请日：2000-01-27
Applicant: KONINKLIJE PHILIPS ELECTRONICS , SONY CORP
Inventor： SCHOUHAMER IMMINK KORNELIS A , ENDEN GIJSBERT J VAN DEN , SHIMPUKU YOSHIHIDE , NAKAMURA KOSUKE , KAHLMAN JOSEPHUS ARNOLDU MARIA , NAKAGAWA TOSHIYUKI , NARAHARA TATSUYA
IPC: H03M7/14 , G06F7/00 , G11B20060101 , G11B5/60 , G11B20/14 , G11B21/21 , H03M20060101 , H03M5/14 , H03M7/00 , H03M7/02 , H03M7/40 , H04L27/00 , H04L27/04 , H03M , G11B
Abstract: A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remainder of division of the "1" count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the "1" count of an element in the code resulting from conversion of the data string by 2.
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27.发明专利
公开(公告)号：HU0003771A2
公开(公告)日：2001-02-28
申请号：HU0003771
申请日：1998-12-07
Applicant: KONINKL PHILIPS ELECTRONICS NV , SONY CORP
Inventor： KAHLMAN JOSEPHUS , NAKAGAWA TOSHIYUKI , NAKAMURA KOUSUKE , NARAHARA TATSUYA , SHIMPUKU YOSHIHIDE
Abstract: An encoder for encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal, the bitstream of the source signal being divided into smaller n-bit source words (x1, x2) which are converted by a logic circuit converter in the encoder into corresponding m-bit channel words, (y1, y2, y3). The conversion of each n-bit source word is parity preserving (see Table I and FIG. 1). The relations hold that m>n>=1, p>=1, and p can vary. Preferably, m=n+1. In order to comply with (d, k) runlength requirements, certain blocks of 2-bit source words are encoded into particular blocks of 3-bit channel words. A decoder is also disclosed for decoding a channel signal produced by the encoder.
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公开(公告)号：DE69423841T2
公开(公告)日：2000-11-16
申请号：DE69423841
申请日：1994-09-20
Applicant: SONY CORP
Inventor： SHIMPUKU YOSHIHIDE
Abstract: An 8->10 modulator (13/22) stores a conversion table, and, when receiving 8-bit data as an address, outputs 10-bit data stored at the received address as a modulated code. The conversion table of the 8->10 modulator is constructed such that each NRZI-represented 10-bit datum includes at least one "0."
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公开(公告)号：BR9806828A
公开(公告)日：2000-05-02
申请号：BR9806828
申请日：1998-09-17
Applicant: KONINKL PHILIPS ELETRONICS N V , SONY CORP
Inventor： KAHLMAN JOSEPHUS ARNOLDUS HENR , IMMINK KORNELIS ANTONIE SCHOUH , ENDEN GIJSBERT JOSEPH VAN DEN , NAKAGAWA TOSHIYUKI , SHIMPUKU YOSHIHIDE , NARAHARA TATSUYA , NAKAMURA KOUSUKE
Abstract: A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C) satisfying a (d,k) constraint, wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (Y1, Y2, Y2). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity preserving (table I). The relations hold that m>n>=1, p>=1, and that p can vary. Preferably, m=n+1. Further, a sync word generator (9) is available for generating a q-bit sync word also satisfying said (d,k) constraint, the said sync word starting with a "0' bit and ending with a "0' bit, the device further comprising merging means (19) for merging said sync word in said stream of databits of the binary channel signal, and that q is an integer value larger than k. (FIG. 1)Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.
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公开(公告)号：DE69420767T2
公开(公告)日：2000-03-02
申请号：DE69420767
申请日：1994-03-17
Applicant: SONY CORP
Inventor： SHIMPUKU YOSHIHIDE , NAKAGAWA TOSHIYUKI
Abstract: There is disclosed a modulating system (30) for converting data of a basic data length of m bits into a variable length code (d, k; m, n; r) of a basic code length of n bits, which comprises the steps of: judging a binding length i (i=1 SIMILAR r) of the basic data; uniformly converting data of mxi bits into a code of nxr bits by using a conversion table for converting data of mxr bits where the binding length i is the maximum binding length r, and including at least one conversion table where the binding length i is less than r; and taking out specific bits from the code of nxr bits thus obtained on the basis of the judged binding length i to output them as a modulation code. Further, there is also disclosed a demodulating system (40) for converting, in reverse direction, a variable length code (d, k; m, n; r) of a basic code length of n bits into data of a basic data length of m bits, comprising the steps of: judging a binding length i of the variable length code; uniformly converting, in reverse direction, a variable length code of nxi bits into data of mxr bits by a reverse conversion table for converting, in reverse direction, a variable length code of nxr bits where the binding length i is the maximum binding length r, and including at least one reverse conversion table where the binding length i is less than r; and taking out specific bits from data thus obtained on the basis of the judged binding length i to output it as reproduction data.
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