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    Multi-phase high-precision current sharing control method applied to constant on-time control
    21.
    发明授权
    Multi-phase high-precision current sharing control method applied to constant on-time control 有权

    公开(公告)号：US12046990B1

    公开(公告)日：2024-07-23

    申请号：US18641384

    申请日：2024-04-21

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Shen Xu ,  Haiqing Zhang ,  Yujie Liu ,  Ruizhi Wang ,  Yuan Gao ,  Yongjia Li ,  Weifeng Sun ,  Longxing Shi

    IPC: H02M1/08 ,  H02M1/00 ,  H02M3/158

    CPC classification number: H02M1/082 ,  H02M1/0025 ,  H02M3/1586

    Abstract: A multi-phase high-precision current sharing control method applied to constant on-time control is provided, wherein a current difference between continuously sampled current of each line and mean current is processed by a PI compensation module and a low-pass filter module to obtain on-time regulation data. A high bit of the regulation data controls the value of counter reference Vref in an on-time control module, and a low bit controls the length of an enabled delay line in a delay line module. The counter timing control of the on-time control module is combined with the delay line timing control of the delay line module to improve the control precision of a DPWM. The method takes COT control of a Buck converter as a typical application. Compared with a multi-phase COT controller without a current-sharing mechanism, the method can improve the stability and reliability of the system.

    Control system for synchronous rectifying transistor of LLC converter
    25.
    发明授权
    Control system for synchronous rectifying transistor of LLC converter 有权

    公开(公告)号：US11201557B2

    公开(公告)日：2021-12-14

    申请号：US16959116

    申请日：2018-12-29

    Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

    Inventor： Qinsong Qian ,  Shengyou Xu ,  Feng Lin ,  Hao Wang ,  Wei Su ,  Qi Liu ,  Longxing Shi

    IPC: H02M3/335 ,  H02M1/00 ,  H02M3/00

    Abstract: A control system for synchronous rectifying transistor of LLC converter, the system comprising a voltage sampling circuit, a high-pass filtering circuit, a PI compensation and effective value detection circuit, and a control system taking a microcontroller (MCU) as a core. When the LLC converter is operating at a high frequency, a drain-source voltage VDS(SR) of the synchronous rectifying transistor delivers, via the sampling circuit, a change signal of the drain-source voltage during turn-off into the high-pass filtering circuit and the PI compensation and effective value detection circuit to obtain an effective value amplification signal of a drain-source voltage oscillation signal caused by parasitic parameters, and the current value is compared with a previously collected value via a control circuit taking a microcontroller (MCU) as a core, so as to change a turning-on time of the synchronous rectifying transistor in the next period.

    Error recovery circuit oriented to CPU pipeline
    27.
    发明授权
    Error recovery circuit oriented to CPU pipeline 有权

    公开(公告)号：US09600382B2

    公开(公告)日：2017-03-21

    申请号：US14442071

    申请日：2013-08-30

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weiwei Shan ,  Chaoxuan Tian ,  Huafang Sun ,  Longxing Shi

    IPC: G06F11/00 ,  G06F11/20 ,  G06F11/30 ,  G06F1/32

    CPC classification number: G06F11/2035 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/1402 ,  G06F11/3024 ,  G06F11/3062 ,  G06F11/3093 ,  G06F2201/805 ,  G06F2201/85 ,  Y02D10/126 ,  Y02D10/172

    Abstract: Disclosed is an error recovery circuit facing a CPU assembly line, comprising: on-chip monitoring circuits (1), an error signal statistics module (2), a voltage frequency control module (3), an error recovery control module (4), an in-situ error recovery module (5) and an upper-layer error recovery module (6), wherein each of the on-chip monitoring circuits (1) is integrated at the end of each stage of assembly lines of the previous N−1 stages of assembly lines of a CPU kernel with an N-stage assembly line structure, so as to monitor the time sequence information about each clock period of an operating circuit, wherein N is a positive integer which is greater than or equal to 3 and less than 20. The present invention provides the on-line time sequence monitoring on the CPU kernel with N stages of assembly lines to search for the lowest possible operating voltage of the circuit, and to reduce the margin of the operating voltage reserved for the circuit in the design stage, thereby significantly reducing the power consumption of the circuit and improving the energy efficiency of the circuit.

    Transverse ultra-thin insulated gate bipolar transistor having high current density
    28.
    发明授权
    Transverse ultra-thin insulated gate bipolar transistor having high current density 有权
    具有高电流密度的横向超薄绝缘栅双极晶体管

    公开(公告)号：US09240469B2

    公开(公告)日：2016-01-19

    申请号：US14439715

    申请日：2012-12-27

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weifeng Sun ,  Jing Zhu ,  Shen Xu ,  Qinsong Qian ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

    IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/49 ,  H01L29/10 ,  H01L29/08 ,  H01L23/528

    CPC classification number: H01L29/7394 ,  H01L23/528 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/1008 ,  H01L29/4916 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.

    Abstract translation: 具有电流密度的横向超薄绝缘栅双极晶体管包括：P基板，其中P基板在其上设置有掩埋氧化物层，所述掩埋氧化物层在其上设置有N外延层，提供N外延层 在其中具有N阱区域和P基极区域，P基极区域中设置有第一P接触区域和N源极区域，N阱区域中设置有N个缓冲区域，N阱区域设置有 在其上的场氧化物层，N缓冲区在其中设置有P漏极区，N外延层中设置有包括P环状基极区的P基区阵列，P基区阵列位于N阱之间 区域和P基区域中，P环状基部区域设置有第二P接触区域和N环状源极区域，第二P接触区域位于N环状源极区域中。 本发明大大增加了横向超薄绝缘栅双极晶体管的电流密度，从而显着提高了智能功率模块的性能。

    Control method for four-switch buck-boost converter
    30.
    发明授权
    Control method for four-switch buck-boost converter 有权

    公开(公告)号：US12062985B1

    公开(公告)日：2024-08-13

    申请号：US18566102

    申请日：2022-09-26

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Qi Liu ,  Weiwei Zhai ,  Leilei Shi ,  Qinsong Qian ,  Weifeng Sun ,  Longxing Shi

    IPC: H02M3/158 ,  H02M1/00 ,  H02M1/088

    CPC classification number: H02M3/1582 ,  H02M1/0058 ,  H02M1/088

    Abstract: A control method for a four-switch buck-boost converter is provided. The control method adopts four-stage control, and divides the load range into two sections and adopts different control strategies according to a critical load value corresponding to optimal control. In Boost mode, before the critical load, T1 and T2 are kept constant, T3 is a minimum value for realizing soft-switching, and T4 decreases with the increase of the load; when the critical load is reached, T4 drops to 0; and after the critical load, T1, T2, T3 and T increase with the load. In Buck mode, before the critical load, T2 and T3 are kept constant, T1 is a minimum value for realizing soft-switching, and T4 decreases with the increase of the load; when the critical load is reached, T4 drops to 0; and after the critical load, T1, T2, T3 and T increase with the load.

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