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    Transverse ultra-thin insulated gate bipolar transistor having high current density
    25.
    发明授权
    Transverse ultra-thin insulated gate bipolar transistor having high current density 有权
    具有高电流密度的横向超薄绝缘栅双极晶体管

    公开(公告)号：US09240469B2

    公开(公告)日：2016-01-19

    申请号：US14439715

    申请日：2012-12-27

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weifeng Sun ,  Jing Zhu ,  Shen Xu ,  Qinsong Qian ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

    IPC: H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/49 ,  H01L29/10 ,  H01L29/08 ,  H01L23/528

    CPC classification number: H01L29/7394 ,  H01L23/528 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/1008 ,  H01L29/4916 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.

    Abstract translation: 具有电流密度的横向超薄绝缘栅双极晶体管包括：P基板，其中P基板在其上设置有掩埋氧化物层，所述掩埋氧化物层在其上设置有N外延层，提供N外延层 在其中具有N阱区域和P基极区域，P基极区域中设置有第一P接触区域和N源极区域，N阱区域中设置有N个缓冲区域，N阱区域设置有 在其上的场氧化物层，N缓冲区在其中设置有P漏极区，N外延层中设置有包括P环状基极区的P基区阵列，P基区阵列位于N阱之间 区域和P基区域中，P环状基部区域设置有第二P接触区域和N环状源极区域，第二P接触区域位于N环状源极区域中。 本发明大大增加了横向超薄绝缘栅双极晶体管的电流密度，从而显着提高了智能功率模块的性能。

    Control method for four-switch buck-boost converter
    26.
    发明授权
    Control method for four-switch buck-boost converter 有权

    公开(公告)号：US12062985B1

    公开(公告)日：2024-08-13

    申请号：US18566102

    申请日：2022-09-26

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Qi Liu ,  Weiwei Zhai ,  Leilei Shi ,  Qinsong Qian ,  Weifeng Sun ,  Longxing Shi

    IPC: H02M3/158 ,  H02M1/00 ,  H02M1/088

    CPC classification number: H02M3/1582 ,  H02M1/0058 ,  H02M1/088

    Abstract: A control method for a four-switch buck-boost converter is provided. The control method adopts four-stage control, and divides the load range into two sections and adopts different control strategies according to a critical load value corresponding to optimal control. In Boost mode, before the critical load, T1 and T2 are kept constant, T3 is a minimum value for realizing soft-switching, and T4 decreases with the increase of the load; when the critical load is reached, T4 drops to 0; and after the critical load, T1, T2, T3 and T increase with the load. In Buck mode, before the critical load, T2 and T3 are kept constant, T1 is a minimum value for realizing soft-switching, and T4 decreases with the increase of the load; when the critical load is reached, T4 drops to 0; and after the critical load, T1, T2, T3 and T increase with the load.

    Gate drive circuit for reducing reverse recovery current of power device
    30.
    发明授权
    Gate drive circuit for reducing reverse recovery current of power device 有权

    公开(公告)号：US11152936B2

    公开(公告)日：2021-10-19

    申请号：US17044623

    申请日：2020-04-15

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Jing Zhu ,  Weifeng Sun ,  Bowei Yang ,  Siyuan Yu ,  Yangyang Lu ,  Longxing Shi

    IPC: H03K3/00 ,  H03K17/08 ,  H03K17/16 ,  H03K17/687 ,  H03K19/20

    Abstract: The present invention discloses a gate drive circuit for reducing a reverse recovery current of a power device, and belongs to the field of basic electronic circuit technologies. The gate drive circuit includes a high-voltage LDMOS transistor, a diode forming a freewheeling path when the diode is turned on or a low-voltage MOS transistor in anti-parallel connection with a body diode, and a voltage detection circuit. When the power device is turned off, a freewheeling current produced by an inductive load flows through a freewheeling diode, the voltage detection circuit detects that the freewheeling diode is turned on, and an output signal is processed by a control circuit, to cause the drive circuit to output a high level, so that channels of the power device and the high-voltage LDMOS transistor are turned on, the freewheeling current flows through the conductive channels, almost not through the freewheeling diode, and there is no reverse recovery current in the freewheeling diode at this time, thereby reducing the reverse recovery current of the power device.

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