公开(公告)号：ES2156269T3

公开(公告)日：2001-06-16

申请号：ES96830472

申请日：1996-09-17

Applicant: ST MICROELECTRONICS SRL ,  MAGNETI MARELLI SPA

Inventor： CRESPI ANGELO ,  CHICCA STEFANIA ,  MASTELLA PAOLO ,  POLETTO VANNI

IPC: G01R15/14 ,  G01R19/00 ,  G01R19/165 ,  G01R31/00 ,  G01R31/02 ,  G01R31/28

Abstract: A circuit for diagnosing the state of a load (LD) comprises a DMOS transistor (DMOS1) interposed between a terminal (OUT) of the load (LD) and voltage comparator circuits (CDT) in order to limit the maximum voltage input to the comparators (CDT) to reduce the circuit area occupied by the comparators (CDT) and consequently the cost of the diagnosis circuit.

公开(公告)号：DE69612282D1

公开(公告)日：2001-05-03

申请号：DE69612282

申请日：1996-09-17

Applicant: ST MICROELECTRONICS SRL ,  MAGNETI MARELLI SPA

Inventor： POLETTO VANNI ,  POMA ALBERTO ,  MORELLI MARCO

IPC: G01F23/00 ,  H03K17/945

Abstract: A circuit for controlling the reserve lamp (LAMP) of a vehicle's fuel level indicator instrument (STR). The circuit uses a switch (SW1) controlled by an extremely asymmetric clock signal (CLK) periodically to switch, for a very short time, the signal (Rj) provided by the level sensor (SENS) towards a comparator (CMP) operable to compare this signal (Rj) with a threshold value (Rth) for the purpose of determining the state of the reserve lamp (LAMP).

公开(公告)号：FR3078415B1

公开(公告)日：2021-09-17

申请号：FR1851699

申请日：2018-02-27

Applicant: ST MICROELECTRONICS SRL ,  ST MICROELECTRONICS INC ,  ST MICROELECTRONICS ALPS SAS

Inventor： POLETTO VANNI ,  SWANSON DAVID F ,  TORRISI GIOVANNI LUCA ,  CHEVALIER LAURENT

IPC: G05F1/565 ,  H01L27/02 ,  H02M1/08

Abstract: L'invention concerne un circuit de commande de transistors (44, 46) en parallèle comprenant au moins deux étages (42, 43) destinés chacun à fournir un signal de commande à un des transistors, dans lequel un courant de sortie de chaque étage est régulé selon la différence entre la somme de valeurs représentatives des courants de sortie mesurés de chaque étage et la somme de valeurs des consignes affectées à tous les étages.

公开(公告)号：DE102017113530A1

公开(公告)日：2018-05-30

申请号：DE102017113530

申请日：2017-06-20

Applicant: ST MICROELECTRONICS SRL

Inventor： POLETTO VANNI ,  PROVINZANO BIAGIO

IPC: H03F3/45

Abstract: Eine (Vor-)Treiberschaltung (100) für z. B. Elektromotoren beinhaltet:einen ersten (Gxy) und einen zweiten (Sxy) Ausgangsanschluss, die mit einem Leistungstransistor (T) koppelbar sind,eine Differenzstufe (10), die einen nicht invertierenden (+) und einen invertierenden (-) Eingang aufweist, zum Aufnehmen einer Eingangsspannung (Vin), wobei die Eingangsspannung (Vin) als eine Ausgangsspannung (Vgs) über dem ersten (Gxy) und dem zweiten (Sxy) Ausgangsanschluss als ein Treibersignal für den Leistungstransistor repliziert wird.Die Differenzstufe (10) umfasst einen Differenz-Transkonduktanz-Verstärker in einer Spannungsfolgeranordnung, die kontinuierliche Regelung der Spannung an dem ersten Ausgangsanschluss (Gxy) relativ zu dem zweiten Ausgangsanschluss (Sxy) vorsieht.

公开(公告)号：DE60102213D1

公开(公告)日：2004-04-08

申请号：DE60102213

申请日：2001-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： POLETTO VANNI

IPC: G05B11/42

Abstract: The present invention relates to a digital control circuit of the P.I. (Proportional Integral) type, receiving an error signal (Error) at an input terminal (IN1) and adapted to provide, at an output terminal (OUT1), a PWM [Pulse Width Modulated] output signal (PWM Output). The circuit is of a type comprising at least one analog-to-digital converter (100, 100*) connected to the input terminal (IN) and to the output terminal (OUT1) through at least one integrative/proportional branch (120, 121, 130, 134). Advantageously in this invention, the analog-to-digital converter (100, 100*) is an integration converter adapted to integrate the error signal (Error) before an analog-to-digital conversion thereof.

公开(公告)号：ES2194091T3

公开(公告)日：2003-11-16

申请号：ES96830610

申请日：1996-12-05

Applicant: ST MICROELECTRONICS SRL ,  MAGNETI MARELLI POWERTRAIN SPA

Inventor： MILANESI ANDREA ,  POLETTO VANNI ,  POMA ALBERTO ,  MORELLI MARCO

IPC: G05F1/575

Abstract: A voltage-regulator circuit with a low voltage drop using a DMOS power transistor (PT) driven by a charge pump (CP) comprises two feedback loops: a first feedback loop having high gain and accuracy but low response speed, and a second feedback loop having a wide passband and fast response speed but low gain.

公开(公告)号：DE69626991D1

公开(公告)日：2003-04-30

申请号：DE69626991

申请日：1996-12-05

Applicant: ST MICROELECTRONICS SRL ,  MAGNETI MARELLI POWERTRAIN SPA

Inventor： MILANESI ANDREA ,  POLETTO VANNI ,  POMA ALBERTO ,  MORELLI MARCO

IPC: G05F1/575

Abstract: A voltage-regulator circuit with a low voltage drop using a DMOS power transistor (PT) driven by a charge pump (CP) comprises two feedback loops: a first feedback loop having high gain and accuracy but low response speed, and a second feedback loop having a wide passband and fast response speed but low gain.

公开(公告)号：DE69611826T2

公开(公告)日：2001-06-07

申请号：DE69611826

申请日：1996-09-17

Applicant: ST MICROELECTRONICS SRL ,  MAGNETI MARELLI SPA

Inventor： CRESPI ANGELO ,  CHICCA STEFANIA ,  MASTELLA PAOLO ,  POLETTO VANNI

IPC: G01R15/14 ,  G01R19/00 ,  G01R19/165 ,  G01R31/00 ,  G01R31/02 ,  G01R31/28

Abstract: A circuit for diagnosing the state of a load (LD) comprises a DMOS transistor (DMOS1) interposed between a terminal (OUT) of the load (LD) and voltage comparator circuits (CDT) in order to limit the maximum voltage input to the comparators (CDT) to reduce the circuit area occupied by the comparators (CDT) and consequently the cost of the diagnosis circuit.

公开(公告)号：DE69611826D1

公开(公告)日：2001-03-29

申请号：DE69611826

申请日：1996-09-17

Applicant: ST MICROELECTRONICS SRL ,  MAGNETI MARELLI SPA

Inventor： CRESPI ANGELO ,  CHICCA STEFANIA ,  MASTELLA PAOLO ,  POLETTO VANNI

IPC: G01R15/14 ,  G01R19/00 ,  G01R19/165 ,  G01R31/00 ,  G01R31/02 ,  G01R31/28

Abstract: A circuit for diagnosing the state of a load (LD) comprises a DMOS transistor (DMOS1) interposed between a terminal (OUT) of the load (LD) and voltage comparator circuits (CDT) in order to limit the maximum voltage input to the comparators (CDT) to reduce the circuit area occupied by the comparators (CDT) and consequently the cost of the diagnosis circuit.

公开(公告)号：DE69227244T2

公开(公告)日：1999-03-04

申请号：DE69227244

申请日：1992-07-28

Applicant: ST MICROELECTRONICS SRL

Inventor： POLETTO VANNI ,  MORELLI MARCO

IPC: H01L29/73 ,  G05F1/569 ,  H01L21/331 ,  H03K17/0422 ,  G05F1/56 ,  H03K17/04

Abstract: Saturation of a bipolar power transistor is controlled by sensing the current which is eventually injected into the substrate of the integrated circuit by the saturating transistor and using this signal for exerting a limiting action on the current which is driven to the base of the power transistor by a dedicated driving circuit. Differently from the prior art antisaturation systems, it is no longer necessary to precisely monitor the operating voltages across the terminals of the bipolar power transistor. A suitable sensing resistance may be integrated conveniently at a distance from the often complex integrated structure of the bipolar transistor. The system of the invention offers numerous advantages and ensures intervention of the antisaturation circuit only when the power transistor has positively reached a state of saturation, but well before any unwanted consequence.