公开(公告)号：US11222969B2

公开(公告)日：2022-01-11

申请号：US16808311

申请日：2020-03-03

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Alfonso Patti

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/10 ,  H01L21/02 ,  H01L29/205 ,  H01L29/417

Abstract: A normally-off electronic device, comprising: a semiconductor body including a heterostructure that extends over a buffer layer; a recessed-gate electrode, extending in a direction orthogonal to the plane; a first working electrode and a second working electrode at respective sides of the gate electrode; and an active area housing, in the on state, a conductive path for a flow of electric current between the first and second working electrodes. A resistive region extends at least in part in the active area that is in the buffer layer and is designed to inhibit the flow of current between the first and second working electrodes when the device is in the off state. The gate electrode extends in the semiconductor body to a depth at least equal to the maximum depth reached by the resistive region.

公开(公告)号：US11043574B2

公开(公告)日：2021-06-22

申请号：US16535016

申请日：2019-08-07

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Paolo Badala'

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/778 ,  C23C14/00 ,  C23C14/06 ,  C23C14/30

Abstract: An HEMT device of a normally-on type, comprising a heterostructure; a dielectric layer extending over the heterostructure; and a gate electrode extending right through the dielectric layer. The gate electrode is a stack, which includes: a protection layer, which is made of a metal nitride with stuffed grain boundaries and extends over the heterostructure, and a first metal layer, which extends over the protection layer and is completely separated from the heterostructure by said protection layer.

公开(公告)号：US10651304B2

公开(公告)日：2020-05-12

申请号：US16526915

申请日：2019-07-30

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano

IPC: H01L31/0256 ,  H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423

Abstract: In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

公开(公告)号：US10566450B2

公开(公告)日：2020-02-18

申请号：US16004272

申请日：2018-06-08

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Giuseppe Greco ,  Fabrizio Roccaforte

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L23/29 ,  H01L23/31 ,  H01L29/737 ,  H01L29/417 ,  H01L29/207

Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.

公开(公告)号：US10032898B2

公开(公告)日：2018-07-24

申请号：US15832680

申请日：2017-12-05

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Andrea Severino ,  Maria Concetta Nicotra ,  Alfonso Patti

IPC: H01L29/778 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

公开(公告)号：US09882040B2

公开(公告)日：2018-01-30

申请号：US15156740

申请日：2016-05-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Andrea Severino ,  Maria Concetta Nicotra ,  Alfonso Patti

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

公开(公告)号：US12062715B2

公开(公告)日：2024-08-13

申请号：US17703779

申请日：2022-03-24

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/778 ,  H01L29/78

CPC classification number: H01L29/7786 ,  H01L29/401 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7838

Abstract: An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.

公开(公告)号：US11854977B2

公开(公告)日：2023-12-26

申请号：US16676371

申请日：2019-11-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Santo Alessandro Smerzi ,  Maria Concetta Nicotra ,  Ferdinando Iucolano

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L23/5286 ,  H01L23/5226 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42316

Abstract: An electronic device, comprising plurality of source metal strips in a first metal level; a plurality of drain metal strips in the first metal level; a source metal bus in a second metal level above the first metal level; a drain metal bus, in the second metal level; a source pad, coupled to the source metal bus; and a drain pad, coupled to the drain metal bus. The source metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the first conductive pad; the drain metal bus includes subregions shaped in such a way that, in top-plan view, each of them has a width which decreases moving away from the second conductive pad. The first and second subregions are interdigitated.

公开(公告)号：US11728404B2

公开(公告)日：2023-08-15

申请号：US17350916

申请日：2021-06-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Paolo Badalá

IPC: H01L29/66 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/778 ,  H01L21/28 ,  C23C14/00 ,  C23C14/06 ,  C23C14/30 ,  H01L29/417

CPC classification number: H01L29/66462 ,  H01L21/28264 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/475 ,  H01L29/66431 ,  H01L29/7786 ,  C23C14/0021 ,  C23C14/0641 ,  C23C14/0676 ,  C23C14/30 ,  H01L29/41766

Abstract: An HEMT device of a normally-on type, comprising a heterostructure; a dielectric layer extending over the heterostructure; and a gate electrode extending right through the dielectric layer. The gate electrode is a stack, which includes: a protection layer, which is made of a metal nitride with stuffed grain boundaries and extends over the heterostructure, and a first metal layer, which extends over the protection layer and is completely separated from the heterostructure by said protection layer.

公开(公告)号：US11101363B2

公开(公告)日：2021-08-24

申请号：US16690035

申请日：2019-11-20

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Alfonso Patti ,  Alessandro Chini

IPC: H01L29/15 ,  H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20

Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.