公开(公告)号：US11699748B2

公开(公告)日：2023-07-11

申请号：US17322528

申请日：2021-05-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Giuseppe Greco ,  Fabrizio Roccaforte

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L23/29 ,  H01L23/31 ,  H01L29/737 ,  H01L29/207 ,  H01L29/417

CPC classification number: H01L29/7786 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/1087 ,  H01L29/207 ,  H01L29/41766 ,  H01L29/7378

Abstract: A normally-off HEMT transistor includes a heterostructure including a channel layer and a barrier layer on the channel layer; a 2DEG layer in the heterostructure; an insulation layer in contact with a first region of the barrier layer; and a gate electrode through the whole thickness of the insulation layer, terminating in contact with a second region of the barrier layer. The barrier layer and the insulation layer have a mismatch of the lattice constant (“lattice mismatch”), which generates a mechanical stress solely in the first region of the barrier layer, giving rise to a first concentration of electrons in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer which is greater than a second concentration of electrons in a second portion of the two-dimensional conduction channel which is under the second region of the barrier layer.

公开(公告)号：US11489068B2

公开(公告)日：2022-11-01

申请号：US17115459

申请日：2020-12-08

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Ferdinando Iucolano ,  Alessandro Chini

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

Abstract: An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain electrode, facing a first side of the gate electrode; and a source electrode, facing a second side opposite to the first side of the gate electrode; an auxiliary channel layer, which extends over the heterojunction structure between the gate electrode and the drain electrode, in electrical contact with the drain electrode and at a distance from the gate electrode, and forming an additional conductive path for charge carriers that flow between the source electrode and the drain electrode.

公开(公告)号：US10050136B2

公开(公告)日：2018-08-14

申请号：US15371012

申请日：2016-12-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano

IPC: H01L31/0256 ,  H01L29/778 ,  H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

Abstract: In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

公开(公告)号：US20170345918A1

公开(公告)日：2017-11-30

申请号：US15371012

申请日：2016-12-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7786

Abstract: In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

公开(公告)号：US12218231B2

公开(公告)日：2025-02-04

申请号：US17116465

申请日：2020-12-09

Applicant: STMicroelectronics S.r.l.

Inventor： Ferdinando Iucolano ,  Alessandro Chini

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66

Abstract: An HEMT transistor includes a semiconductor body having a semiconductive heterostructure. A gate region, of conductive material, is arranged above and in contact with the semiconductor body. A first insulating layer extends over the semiconductor body, laterally to the conductive gate region. A second insulating layer extends over the first insulating layer and the gate region. A first field plate region, of conductive material, extends between the first and the second insulating layers, laterally spaced from the conductive gate region along a first direction. A second field plate region, of conductive material, extends over the second insulating layer, and the second field plate region overlies and is vertically aligned with the first field plate region.

公开(公告)号：US12165871B2

公开(公告)日：2024-12-10

申请号：US17083181

申请日：2020-10-28

Applicant: STMicroelectronics S.r.l.

Inventor： Ferdinando Iucolano ,  Cristina Tringali

IPC: H01L29/778 ,  H01L21/285 ,  H01L21/3213 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/66

Abstract: A method for manufacturing a HEMT device includes forming, on a heterostructure, a dielectric layer, forming a through opening through the dielectric layer, and forming a gate electrode in the through opening. Forming the gate electrode includes forming a sacrificial structure, depositing by evaporation a first gate metal layer layer, carrying out a lift-off of the sacrificial structure, depositing a second gate metal layer by sputtering, and depositing a third gate metal layer. The second gate metal layer layer forms a barrier against the diffusion of metal atoms towards the heterostructure.

公开(公告)号：US10411123B2

公开(公告)日：2019-09-10

申请号：US16036597

申请日：2018-07-16

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano

IPC: H01L21/331 ,  H01L21/8222 ,  H01L29/778 ,  H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

Abstract: In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

公开(公告)号：US20180342606A1

公开(公告)日：2018-11-29

申请号：US16036597

申请日：2018-07-16

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/778 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7786

Abstract: In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

公开(公告)号：US20180108767A1

公开(公告)日：2018-04-19

申请号：US15832680

申请日：2017-12-05

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Andrea Severino ,  Maria Concetta Nicotra ,  Alfonso Patti

IPC: H01L29/778 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.

公开(公告)号：US20170141218A1

公开(公告)日：2017-05-18

申请号：US15156740

申请日：2016-05-17

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Ferdinando Iucolano ,  Andrea Severino ,  Maria Concetta Nicotra ,  Alfonso Patti

IPC: H01L29/778 ,  H01L29/205 ,  H01L21/28 ,  H01L29/417 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/28264 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.