公开(公告)号：US20130228822A1

公开(公告)日：2013-09-05

申请号：US13774554

申请日：2013-02-22

Applicant: STMICROELECTRONICS (TOURS) SAS ,  UNIVERSITE FRANCOIS RABELAIS UFR SCIENCES ET TECHNIQUES

Inventor： Samuel Menard ,  Yannick Hague ,  Gaël Gautier

IPC: H01L29/747

CPC classification number: H01L29/747 ,  H01L24/32 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/66386 ,  H01L2224/32014

Abstract: A vertical power component including a silicon substrate of a first conductivity type and, on the side of a lower surface supporting a single electrode, a well of the second conductivity type, in which the component periphery includes, on the lower surface side, a peripheral trench at least partially filled with a passivation and, between the well and the trench, a porous silicon insulating ring.

Abstract translation: 一种垂直功率分量，包括第一导电类型的硅衬底，并且在支撑单个电极的下表面侧，在所述下表面侧具有第二导电类型的阱，所述第二导电类型的阱在所述下表面侧具有周边 至少部分地填充有钝化物的沟槽，以及阱和沟槽之间的多孔硅绝缘环。

公开(公告)号：US10453835B2

公开(公告)日：2019-10-22

申请号：US16055635

申请日：2018-08-06

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L29/66 ,  H01L21/332 ,  H01L27/02 ,  H01L29/74 ,  H01L29/747 ,  H01L29/87 ,  H01L29/417 ,  H01L29/423

Abstract: A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first portion resting on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main metallization rests on a portion of the layer. A gate metallization on the upper surface side rests on a second region of the first conductivity type formed in the layer in the vicinity of the first region. A porous silicon bar formed in the layer at the upper surface side has a first end in contact with the gate metallization and a second end in contact with the main metallization.

公开(公告)号：US10211326B2

公开(公告)日：2019-02-19

申请号：US15362919

申请日：2016-11-29

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L29/747 ,  H01L29/66 ,  H01L29/40

Abstract: A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate.

公开(公告)号：US09780188B2

公开(公告)日：2017-10-03

申请号：US15354496

申请日：2016-11-17

Applicant: STMicroelectronics (Tours) SAS ,  Universite Francois Rabelais

Inventor： Samuel Menard ,  Gael Gautier

IPC: H01L29/747 ,  H01L29/66 ,  H01L29/87 ,  H01L29/06 ,  H01L21/288 ,  H01L21/762 ,  H01L29/32 ,  H01L29/45

CPC classification number: H01L29/66386 ,  H01L21/2885 ,  H01L21/76202 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/32 ,  H01L29/456 ,  H01L29/747 ,  H01L29/87

Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well. The porous silicon ring is produced by forming a doped well in a first surface of a doped substrate, placing that first surface of the substrate into an electrolytic bath, and circulating a current between an opposite second surface of the substrate and the electrolytic bath.

公开(公告)号：US20170069733A1

公开(公告)日：2017-03-09

申请号：US15354496

申请日：2016-11-17

Applicant: STMicroelectronics (Tours) SAS ,  Universite Francois Rabelais

Inventor： Samuel Menard ,  Gael Gautier

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/32 ,  H01L21/288 ,  H01L29/747 ,  H01L29/45

CPC classification number: H01L29/66386 ,  H01L21/2885 ,  H01L21/76202 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/32 ,  H01L29/456 ,  H01L29/747 ,  H01L29/87

Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well. The porous silicon ring is produced by forming a doped well in a first surface of a doped substrate, placing that first surface of the substrate into an electrolytic bath, and circulating a current between an opposite second surface of the substrate and the electrolytic bath.

Abstract translation: 垂直功率部件包括在衬底的下表面上具有第二导电类型的阱的第一导电类型的硅衬底。 第一个阱在具有绝缘多孔硅环的部件周边上界定。 多孔硅环的上表面仅与第一导电类型的基板接触。 绝缘多孔硅环穿透衬底直至深度大于孔的厚度。 多孔硅环通过在掺杂衬底的第一表面中形成掺杂阱，将衬底的第一表面放置在电解槽中并使电流在衬底的相对的第二表面和电解槽之间循环来制造。

公开(公告)号：US20160027907A1

公开(公告)日：2016-01-28

申请号：US14731563

申请日：2015-06-05

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard ,  Dalaf Ali

IPC: H01L29/747

CPC classification number: H01L29/747 ,  H01L29/0638

Abstract: A bidirectional switch is formed in a semiconductor substrate of a first conductivity type. The switch includes first and second thyristors connected in antiparallel extending vertically between front and rear surfaces of the substrate. A vertical peripheral wall of the second conductivity type connects the front surface to the rear surface and surrounds the thyristors. On the front surface, in a ring-shaped region of the substrate separating the vertical peripheral wall from the thyristors, a first region of the first conductivity type is provided having a doping level greater than the substrate and having the shape of a ring-shaped band portion partially surrounding the first thyristor and stopping at the level of the adjacent region between the first and second thyristors.

Abstract translation: 在第一导电类型的半导体衬底中形成双向开关。 该开关包括第一和第二晶闸管，其在基板的前表面和后表面之间垂直地反向平行地延伸。 第二导电类型的垂直周壁将前表面连接到后表面并围绕晶闸管。 在前表面上，在将垂直周壁与晶闸管分离的衬底的环形区域中，提供第一导电类型的第一区域，其具有大于衬底的掺杂水平，并且具有环形形状 带部分部分地围绕第一晶闸管并且在第一和第二晶闸管之间的相邻区域的水平处停止。

公开(公告)号：US20150084094A1

公开(公告)日：2015-03-26

申请号：US14494692

申请日：2014-09-24

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard

IPC: H01L29/74 ,  H01L21/322 ,  H01L21/02 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/74 ,  H01L21/2807 ,  H01L21/306 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/102 ,  H01L29/32 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66363 ,  H01L29/66545 ,  H01L29/7408

Abstract: An SCR-type component of vertical structure has a main upper electrode formed on a silicon region of a first conductivity type which is formed in a silicon layer of a second conductivity type. The silicon region is interrupted in first areas where the material of the silicon layer comes into contact with the upper electrode, and is further interrupted in second areas filled with resistive porous silicon extending between the silicon layer and the main upper electrode.

Abstract translation: 垂直结构的SCR型分量具有形成在第二导电类型的硅层中的形成在第一导电类型的硅区上的主上电极。 在硅层的材料与上电极接触的第一区域中，硅区被中断，并且在硅层和主上电极之间延伸的第二区填充有电阻性多孔硅，进一步中断。

公开(公告)号：US09530875B2

公开(公告)日：2016-12-27

申请号：US14990194

申请日：2016-01-07

Applicant: STMicroelectronics (Tours) SAS ,  Universite Francois Rabelais

Inventor： Samuel Menard ,  Gael Gautier

IPC: H01L29/747 ,  H01L29/87 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/66386 ,  H01L21/2885 ,  H01L21/76202 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/32 ,  H01L29/456 ,  H01L29/747 ,  H01L29/87

Abstract: A vertical power component includes a silicon substrate of a first conductivity type with a well of the second conductivity type on a lower surface of the substrate. The first well is bordered at a component periphery with an insulating porous silicon ring. An upper surface of the porous silicon ring is only in contact with the substrate of the first conductivity type. The insulating porous silicon ring penetrates into the substrate down to a depth greater than a thickness of the well.

公开(公告)号：US20160027774A1

公开(公告)日：2016-01-28

申请号：US14730826

申请日：2015-06-04

Applicant: STMicroelectronics (Tours) SAS

Inventor： Samuel Menard ,  Dalaf Ali

IPC: H01L27/08 ,  H01L23/528

CPC classification number: H01L27/0817 ,  H01L23/528 ,  H01L29/0834 ,  H01L29/747 ,  H01L2924/0002 ,  H01L2924/13033 ,  H01L2924/00

Abstract: A bidirectional switch formed in a substrate includes first and second main vertical thyristors in antiparallel connection. A third auxiliary vertical thyristor has a rear surface layer in common with the rear surface layer of the first thyristor. A peripheral region surrounds the thyristors and connects the rear surface layer to a layer of the same conductivity type of the third thyristor located on the other side of the substrate. A metallization connects the rear surfaces of the first and second thyristors. An insulating structure is located between the rear surface layer of the third thyristor and the metallization. The insulating structure extends under the periphery of the first thyristor. The insulating structure includes a region made of an insulating material and a complementary region made of a semiconductor material.

Abstract translation: 形成在衬底中的双向开关包括反并联连接的第一和第二主垂直晶闸管。 第三辅助垂直晶闸管具有与第一晶闸管的后表面层共同的后表面层。 周边区域围绕晶闸管并且将后表面层连接到位于基板另一侧上的与第三晶闸管相同的导电类型的层。 金属化连接第一和第二晶闸管的后表面。 绝缘结构位于第三晶闸管的后表面层与金属化之间。 绝缘结构在第一晶闸管的外围延伸。 绝缘结构包括由绝缘材料制成的区域和由半导体材料制成的互补区域。

公开(公告)号：US08994065B2

公开(公告)日：2015-03-31

申请号：US13901494

申请日：2013-05-23

Applicant: STMicroelectronics (Tours) SAS ,  Universite Francois Rabelais

Inventor： Samuel Menard ,  Gaël Gautier

IPC: H01L29/747 ,  H01L29/74 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/74 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0661 ,  H01L29/66386 ,  H01L29/747

Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.

Abstract translation: 一种垂直功率分量，包括：第一导电类型的硅衬底; 在支撑单个电极的基板的下表面侧，具有第二导电类型的下层; 并且在支撑导电电极和栅电极的基板的上表面侧，具有第二导电类型的上部区域，其中，所述元件周边在下表面上包括穿入基板的多孔硅绝缘环 下降到比下层更深的深度。