公开(公告)号：EP0702242B1

公开(公告)日：2004-01-14

申请号：EP95305862.5

申请日：1995-08-22

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G01R31/3173 ,  G01R31/3185 ,  G06F11/24 ,  G06F11/267 ,  H03K3/037

CPC classification number: G06F11/2236 ,  G01R31/318541 ,  G01R31/318552 ,  H03K3/0375

公开(公告)号：EP0702240B1

公开(公告)日：2003-03-12

申请号：EP95305860.9

申请日：1995-08-22

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G01R31/3173 ,  G01R31/3185 ,  G06F11/24 ,  G06F11/267 ,  H03K3/037

CPC classification number: G06F11/2236 ,  G01R31/318541 ,  H03K3/0375

公开(公告)号：EP0840220B1

公开(公告)日：2002-07-10

申请号：EP97308310.8

申请日：1997-10-20

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G06F11/00

CPC classification number: G06F11/3656 ,  G06F9/4401 ,  G06F11/1417

公开(公告)号：EP0849670B1

公开(公告)日：2001-08-22

申请号：EP97310080.3

申请日：1997-12-12

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G06F11/00

CPC classification number: G06F11/3636 ,  G06F11/3648

公开(公告)号：EP1041390A1

公开(公告)日：2000-10-04

申请号：EP00301289.5

申请日：2000-02-18

Applicant: STMicroelectronics Limited

Inventor： Warren, Robert

IPC: G01R31/3185

CPC classification number: G01R31/318552

Abstract: An integrated circuit comprises a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic, a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins, the test access port controller being connectable to the test logic in a first mode of operation to effect communication of serial test data off-chip, a data adaptor which is connectable to the input and output pins via the test access port controller in a second mode of operation, wherein the data adaptor comprises a first interface for communicating data in the form of serial bits to and from said test access port controller under the control of a first clock signal and a second interface for communicating data in the form of successive sets of parallel data and control signals to and from said on-chip functional circuitry under the control of a second clock signal generated independently of said first clock signal, and wherein said data adaptor comprises data storage means for holding data received in the data adaptor to take into account differences between the first and second clock signals.

Abstract translation: 集成电路包括串行数据输入引脚和串行数据输出引脚，片上功能电路和测试逻辑，连接的测试访问端口控制器，用于通过所述输入和输出引脚在芯片边界上实现串行数据的通信，测试 访问端口控制器可以在第一操作模式下连接到测试逻辑，以实现片外串行测试数据的通信，数据适配器可以通过第二操作模式经由测试访问端口控制器连接到输入和输出引脚 ，其中所述数据适配器包括用于在第一时钟信号的控制下以串行比特的形式传送来自所述测试访问端口控制器的数据的第一接口和用于以连续的并行数据集合的形式传送数据的第二接口 以及在独立于所述第一时钟信号产生的第二时钟信号的控制下控制来自所述片上功能电路的信号，以及w 这里所述数据适配器包括用于保存数据适配器中接收的数据以考虑第一和第二时钟信号之间的差异的数据存储装置。