中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

25 records (took 0.025 seconds)

    Synchronous data adaptor
    1.
    发明授权
    Synchronous data adaptor 有权
    Synchrondatenadapter

    公开(公告)号：EP1041390B1

    公开(公告)日：2005-04-13

    申请号：EP00301289.5

    申请日：2000-02-18

    Applicant: STMicroelectronics Limited

    Inventor： Warren, Robert

    IPC: G01R31/3185

    CPC classification number: G01R31/318552

    Abstract: An integrated circuit comprises a serial data input pin and a serial data output pin, on-chip functional circuitry and test logic, a test access port controller connected to effect communication of serial data across the chip boundary via said input and output pins, the test access port controller being connectable to the test logic in a first mode of operation to effect communication of serial test data off-chip, a data adaptor which is connectable to the input and output pins via the test access port controller in a second mode of operation, wherein the data adaptor comprises a first interface for communicating data in the form of serial bits to and from said test access port controller under the control of a first clock signal and a second interface for communicating data in the form of successive sets of parallel data and control signals to and from said on-chip functional circuitry under the control of a second clock signal generated independently of said first clock signal, and wherein said data adaptor comprises data storage means for holding data received in the data adaptor to take into account differences between the first and second clock signals.

    Trigger sequencing controller
    3.
    发明授权
    Trigger sequencing controller 失效
    触发信号序列的控制装置

    公开(公告)号：EP0862115B1

    公开(公告)日：2001-12-19

    申请号：EP98300031.6

    申请日：1998-01-06

    Applicant: STMicroelectronics Limited

    Inventor： Warren, Robert

    IPC: G06F11/00

    CPC classification number: G06F11/3466 ,  G06F11/348

    Abstract: There is disclosed a single chip integrated circuit device including on-chip functional circuitry and a plurality of diagnostic units connected to monitor the on-chip functional circuitry. The plurality of diagnostic units detect respective trigger conditions by comparing signals from the on-chip functional circuitry with data held in respective diagnostic registers of the diagnostic units. The single chip integrated circuit device further includes trigger sequence control circuitry arranged to receive the trigger conditions and to initiate a trigger message when a predetermined sequence of the trigger conditions is detected. There is also disclosed a method of controlling such trigger sequences.

    A method of effecting communication using a test access port (TAP) controller
    4.
    发明授权
    A method of effecting communication using a test access port (TAP) controller 失效
    用于测试访问端口控制器的消息传输方法（TAP）

    公开(公告)号：EP0840134B1

    公开(公告)日：2007-05-16

    申请号：EP97308311.6

    申请日：1997-10-20

    Applicant: STMicroelectronics Limited

    Inventor： Warren, Robert

    IPC: G01R31/3185

    CPC classification number: G01R31/318555 ,  G01R31/318572

    Abstract: There is disclosed a test access port controller for effecting communications across a chip boundary having a test mode and a diagnostic mode of operation, wherein in the test mode of operation the test data is resultant data from a test operation having an expected and time delayed relationship, and in the diagnostic mode of operation diagnostic data is conveyed both on and off chip in the form of respective independent input and output serial bit streams simultaneously through the test access port controller.

    An integrated circuit with multiple processing cores
    7.
    发明公开
    An integrated circuit with multiple processing cores 有权
    Integrierte Schaltung mit mehreren Prozessorkernen

    公开(公告)号：EP0982595A1

    公开(公告)日：2000-03-01

    申请号：EP99306192.8

    申请日：1999-08-04

    Applicant: STMicroelectronics Limited

    Inventor： Warren, Robert

    IPC: G01R31/3185 ,  G06F11/00

    CPC classification number: G06F11/267

    Abstract: An integrated circuit comprises a serial data input pin and a serial data output pin, on-chip functional circuitry comprising at least two processing cores, a data adaptor which is in communication with the processing cores by respective communication channels and is connectable to the input and output pins, wherein the data adaptor comprises transmit circuitry including means for receiving parallel data and control signals from said on-chip functional circuitry and means for converting said parallel data and control signals into a sequence of serial bits including flow control bits, data bits and channel identification bits which identify the communication channel on which said parallel data and control signals were received and receive circuitry including means for receiving from off-chip via the serial data input pin a sequence of serial bits including flow control bits, data bits and channel identification bits, means for converting said sequence into parallel data and control signals for said on-chip functional circuitry and means for transmitting said parallel data and control signals on the communication channel identified by said channel identification bits.

    Abstract translation: 集成电路包括串行数据输入引脚和串行数据输出引脚，片上功能电路，包括至少两个处理核心，数据适配器，其通过各个通信信道与处理核心通信，并且可连接到输入和 输出引脚，其中所述数据适配器包括发射电路，包括用于从所述片上功能电路接收并行数据和控制信号的装置，以及用于将所述并行数据和控制信号转换成串行位序列的装置，包括流控制位，数据位和 识别所述并行数据和控制信号被接收的通信信道的信道识别位和接收电路，其包括用于经由串行数据输入引脚从芯片外接收包括流控制位，数据位和信道识别的串行比特序列的装置 位，用于将所述序列转换为并行数据和控制符号的装置 用于所述片上功能电路和用于在由所述信道标识位标识的通信信道上发送所述并行数据和控制信号的装置。

Patent Agency Ranking