公开(公告)号：EP0889591A1

公开(公告)日：1999-01-07

申请号：EP97830327.9

申请日：1997-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Scian, Enrico ,  Martignoni, Fabrizio ,  Depetro, Riccardo

IPC: H03K17/10 ,  H03K19/003 ,  G05F3/20 ,  H01L27/02

CPC classification number: H03K19/00315 ,  G05F3/205 ,  H01L27/0251

Abstract: The invention relates to a method, and related circuit, for preventing the triggering of a parasitic transistor in an output stage (2) of an electronic circuit, said stage (2) comprising a transistor pair (M1,M2) with at least one transistor (M2) of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor (3) having a terminal connected to said body terminal, characterized in that it comprises the steps of:

providing a capacitor (C1) connected between the body and source terminals of the PMOS transistor;
using a control circuit (5) to suppress the body effect of the pull-up PMOS transistor.

Abstract translation: 本发明涉及一种方法，以及相关的电路，用于在一个电子电路的输出级（2）防止寄生晶体管的触发，所述步骤（2）包括一个晶体管对（M1，M2），具有至少一个晶体管 上拉PMOS的（M2）型具有respectivement源极，栅极和漏极端子和主体端子，和（3），其具有连接到所述主体端子的端子，在做了它包括以下步骤为特征的寄生双极晶体管：提供 连接在PMOS晶体管的体端子与源极端之间的电容器（C1）; 使用控制电路（5），以抑制PMOS上拉晶体管的体效应。

公开(公告)号：EP0676802B1

公开(公告)日：1998-12-23

申请号：EP94830160.1

申请日：1994-03-31

Applicant: STMicroelectronics S.r.l.

Inventor： Palmieri, Michele ,  Depetro, Riccardo

IPC: H01L21/82 ,  H01L21/329 ,  H01L27/06

CPC classification number: H01L29/66106 ,  H01L21/2253 ,  H01L21/822 ,  H01L27/0617 ,  H01L29/66272 ,  H01L29/66901 ,  H01L29/7304 ,  H01L29/866