公开(公告)号：EP0913927B1

公开(公告)日：2004-10-06

申请号：EP97830561.3

申请日：1997-10-31

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo ,  Martignoni, Fabrizio ,  Scian, Enrico

IPC: H03F1/00 ,  H03K19/0185

CPC classification number: H03K19/018585

公开(公告)号：EP0913925B1

公开(公告)日：2004-10-06

申请号：EP97830559.7

申请日：1997-10-31

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo ,  Martignoni, Fabrizio ,  Scian, Enrico

IPC: H03F1/00 ,  H03K19/0185

CPC classification number: H03K19/018585

公开(公告)号：EP0741416B1

公开(公告)日：2001-09-26

申请号：EP95830176.4

申请日：1995-05-02

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo ,  Contiero, Claudio ,  Andreini, Antonio

IPC: H01L29/00 ,  H01L27/092 ,  H01L27/06

CPC classification number: H01L29/0878 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

公开(公告)号：EP2264753A3

公开(公告)日：2011-04-20

申请号：EP10183038.8

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

IPC: H01L21/76 ,  H01L21/84 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

Abstract: A method is proposed for manufacturing an integrated electronic device (500). The method includes the steps of providing an SOI substrate (505) including a semiconductor substrate (510), an insulating layer (515) on the semiconductor substrate, and a semiconductor starting layer (512) on the insulating layer, the substrate and the starting layer being of a first type of conductivity, performing an epitaxial growing process, the epitaxial growing process being applied to the starting layer to obtain a thicker semiconductor active layer (542) of the first type of conductivity embedding the starting layer on the insulating layer, forming at least one insulating trench (558) extending from an exposed surface of the active layer to the insulating layer, the at least one insulating trench partitioning the active layer into insulated regions (560) and at least one further insulated region (561), and integrating components (580) of the device in the insulated regions, the components being insulated from the substrate by the insulating layer; in the solution according to an embodiment of the invention, the method further includes, before the step of performing an epitaxial growing process, forming at least one contact trench (520) extending from an exposed surface of the starting layer to the substrate in correspondence to each further insulated region, each contact trench clearing a corresponding portion (530b,530s) of the starting layer, of the insulating layer and of the substrate, implanting dopants of a second type of conductivity different from the first type into at least part of the cleared portions, wherein the epitaxial growing is further applied to the cleared portions thereby at least partially filling each contact trench with semiconductor material, the dopants diffusing during the epitaxial growing to form an insulating region (545) of the second type of conductivity enclosing the at least one contact trench of each further insulated region, and integrating further components (580) of the device in each further insulated region, the further components being insulated from the substrate by a junction formed by the corresponding insulating region with the active layer and/or the substrate when reverse-biased.

公开(公告)号：EP2264752A3

公开(公告)日：2011-04-20

申请号：EP10182985.1

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

IPC: H01L21/322 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

Abstract: A method is proposed for manufacturing an integrated electronic device (400) of the SOI type. The method includes the steps of providing an SOI substrate (105) including a semiconductor substrate (110), an insulating layer (115) on the semiconductor substrate, and a semiconductor starting layer (112) on the insulating layer, performing an epitaxial growing process, the epitaxial growing process being applied to the starting layer to obtain a thicker semiconductor active layer (142) embedding the starting layer on the insulating layer, forming at least one insulating trench (405) extending from an exposed surface of the active layer to the insulating layer, the at least one insulating trench partitioning the active layer into insulated regions (415) and at least one further insulated region (425), and integrating components (420) of the device in the insulated regions; in the solution according to an embodiment of the invention, the method further includes, before the step of performing an epitaxial growing process, forming at least one contact trench (120) extending from an exposed surface of the starting layer to the substrate in correspondence to each further insulated region, wherein each contact trench clears a corresponding portion (130b,130s) of the starting layer, of the insulating layer and of the substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling each contact trench with semiconductor material gettering impurities of the active layer, the gettered impurities in the at least one further insulated region being segregated from the insulated regions.

公开(公告)号：EP1873821A1

公开(公告)日：2008-01-02

申请号：EP06116123.8

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

IPC: H01L21/74

CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

Abstract: A method for manufacturing an integrated electronic device (100;400;500) is proposed. The method comprises the steps of: providing an SOI substrate (105;505) comprising a semiconductor substrate (110;510), an insulating layer (115;515) on the semiconductor substrate, and a semiconductor starting layer (112;512) on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer (142;542) on the insulating layer for integrating components of the device, and forming at least one contact trench (120;520) extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion (130b,130s;530b,530s) of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

Abstract translation: 提出了一种用于制造集成电子装置（100; 400; 500）的方法。 该方法包括以下步骤：提供包括半导体衬底（110; 510），半导体衬底上的绝缘层（115; 515）和半导体起始层（112; 512）上的SOI衬底（105; 505） 绝缘层; 外延生长所述起始层以在所述绝缘层上获得半导体有源层（142; 542），用于对所述器件的部件进行积分，以及形成从所述起始层的暴露表面延伸到所述至少一个接触沟槽（120; 520） 在外延生长起始层的步骤之前的半导体衬底，其中每个接触沟槽清除起始层，绝缘层和半导体衬底的对应部分（130b，130s; 530b，530s），外延生长被进一步应用 到清除部分，从而至少部分地用半导体材料填充至少一个接触沟槽。

公开(公告)号：EP1296380B1

公开(公告)日：2007-11-28

申请号：EP01830595.3

申请日：2001-09-20

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo ,  Manzini, Stefano

IPC: H01L29/94

CPC classification number: H01L29/417 ,  H01L29/94

公开(公告)号：EP1195815A1

公开(公告)日：2002-04-10

申请号：EP00830658.1

申请日：2000-10-06

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo

IPC: H01L27/08

CPC classification number: H01L28/10 ,  H01L27/08

Abstract: An inductive structure (1) integrated in a semiconductor substrate (2), comprising at least a conductive element (3) insulated from the substrate (2), comprising an insulating structure (4), which is formed inside said semiconductor substrate (2) and built close to said conductor element (3), so that the resistance of said substrate (2) is increased and the parasitic currents induced by the conductor element (3) in the substrate (2) are decreased.

Abstract translation: 一种集成在半导体衬底（2）中的电感结构（1），包括至少一个与衬底（2）绝缘的导电元件（3），包括形成在所述半导体衬底（2）内部的绝缘结构（4） 并且靠近所述导体元件（3）构建，使得所述衬底（2）的电阻增加，并且由衬底（2）中的导体元件（3）感应的寄生电流减小。

公开(公告)号：EP0913927A1

公开(公告)日：1999-05-06

申请号：EP97830561.3

申请日：1997-10-31

Applicant: STMicroelectronics S.r.l.

Inventor： Depetro, Riccardo ,  Martignoni, Fabrizio ,  Scian, Enrico

IPC: H03F1/00 ,  H03K19/0185

CPC classification number: H03K19/018585

Abstract: The invention relates to an electronic level shifter circuit (1) for driving a high-voltage output stage (2). This output stage (2) comprises a complementary pair (3) of transistors (I36,I32) connected between first (Vdd) and second (Vss) supply voltage references, and at least one PMOS pull-up transistor (I32) connected in series with an NMOS pull-down transistor (I36). An additional transistor (I34) is connected in parallel with the pull-up transistor (I32), and the driver circuit (1) has a first output (A) connected to the control terminal of the pull-up transistor (I32) and a second output connected to the control terminal of the additional transistor (I34).

Abstract translation: 本发明涉及用于驱动高压输出级（2）的电子电平移位器电路（1）。 该输出级（2）包括连接在第一（Vdd）和第二（Vss）电源电压基准之间的晶体管（I36，I32）的互补对（3）和至少一个串联连接的PMOS上拉晶体管（I32） 用NMOS下拉晶体管（I36）。 附加晶体管（I34）与上拉晶体管（I32）并联连接，并且驱动器电路（1）具有连接到上拉晶体管（I32）的控制端子的第一输出（A）和 第二输出端连接到附加晶体管（I34）的控制端。

公开(公告)号：EP2264752A2

公开(公告)日：2010-12-22

申请号：EP10182985.1

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

IPC: H01L21/74 ,  H01L21/84 ,  H01L29/06

CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

Abstract: A method is proposed for manufacturing an integrated electronic device (400) of the SOI type. The method includes the steps of providing an SOI substrate (105) including a semiconductor substrate (110), an insulating layer (115) on the semiconductor substrate, and a semiconductor starting layer (112) on the insulating layer, performing an epitaxial growing process, the epitaxial growing process being applied to the starting layer to obtain a thicker semiconductor active layer (142) embedding the starting layer on the insulating layer, forming at least one insulating trench (405) extending from an exposed surface of the active layer to the insulating layer, the at least one insulating trench partitioning the active layer into insulated regions (415) and at least one further insulated region (425), and integrating components (420) of the device in the insulated regions; in the solution according to an embodiment of the invention, the method further includes, before the step of performing an epitaxial growing process, forming at least one contact trench (120) extending from an exposed surface of the starting layer to the substrate in correspondence to each further insulated region, wherein each contact trench clears a corresponding portion (130b,130s) of the starting layer, of the insulating layer and of the substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling each contact trench with semiconductor material gettering impurities of the active layer, the gettered impurities in the at least one further insulated region being segregated from the insulated regions.

Abstract translation: 提出了一种制造SOI型集成电子器件（400）的方法。 该方法包括以下步骤：提供包括半导体衬底（110），半导体衬底上的绝缘层（115）和绝缘层上的半导体起始层（112）的SOI衬底（105），执行外延生长工艺 ，外延生长工艺被施加到起始层，以获得将起始层嵌入绝缘层上的更厚的半导体有源层（142），形成从活性层的暴露表面延伸到至少一个绝缘沟槽（405） 绝缘层，所述至少一个绝缘沟槽将所述有源层分隔成绝缘区域（415）和至少一个另外的绝缘区域（425），以及将所述器件的部件（420）集成在所述绝缘区域中; 在根据本发明的实施例的解决方案中，该方法还包括在进行外延生长工艺的步骤之前，形成从起始层的暴露表面延伸到衬底的至少一个接触沟槽（120），对应于 每个另外的绝缘区域，其中每个接触沟槽清除起始层，绝缘层和衬底的对应部分（130b，130s），外延生长被进一步施加到清除部分，从而至少部分地填充每个接触沟槽 利用吸收有源层的杂质的半导体材料，至少一个另外的绝缘区域中的杂质杂质与绝缘区域分离。