公开(公告)号：EP1811579A1

公开(公告)日：2007-07-25

申请号：EP06425019.4

申请日：2006-01-18

Applicant: STMicroelectronics S.r.l.

Inventor： Guerra, Ranieri ,  Leonardi, Salvatore

IPC: H01L31/173 ,  H01L27/32

CPC classification number: H01L31/173 ,  H01L51/50 ,  H01L2224/73265 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A galvanic optocoupler structure (10) of the type comprising at least one optical source (3) coupled to an optical detector (5) and separated therefrom by a transmission means (4) of an optical signal is described. Advantageously, the optical source (3) is realised by means of an organic LED comprising a optical substrate (4) transparent with respect to the optical signal and associated directly with the optical detector (5) to serve as transmission and insulation means (4) between the optical source (3) and the optical detector (5).
The hybrid integration process of such a galvanic optocoupler structure is also described.

Abstract translation: 描述了包括耦合到光学检测器（5）并由光信号的传输装置（4）分离的至少一个光源（3）的类型的电流光耦合器结构（10）。 有利地，光源（3）通过有机LED实现，该有机LED包括相对于光信号透明并与光学检测器（5）直接相关的光学基板（4），用作传输和绝缘装置（4） 在光源（3）和光学检测器（5）之间。 还描述了这种电流光耦合器结构的混合集成过程。

公开(公告)号：EP1804326A1

公开(公告)日：2007-07-04

申请号：EP06425001.2

申请日：2006-01-02

Applicant: STMicroelectronics S.r.l.

Inventor： Spoto, Giuseppe Emanuele ,  Giuffrida, Roberta ,  Leonardi, Salvatore ,  Abbisso, Salvatore

IPC: H01M8/24 ,  H01M8/10

CPC classification number: H01M8/2484 ,  H01M8/1011 ,  H01M8/2485 ,  H01M2008/1095 ,  H01M2250/30 ,  Y02B90/18 ,  Y02E60/523 ,  Y02P70/56

Abstract: A flow connector for a microfluidic system through which a solution of at least an oxidable compound is fed to a feed manifold (3) of an energy converting electrochemical device (FC) having a flat coupling area with the flow connector is made as a distinct article of manufacture applicable onto the electrochemical device. The flow connector comprises
a monocrystalline silicon platform (1) having at least two distinct channels (5, 6) defined on the bottom side of the platform, on the top side of which a plurality of functional modules (P, C1, C2, C3, V1, V2, V3) of said microfluidic system are fixed in correspondence of respective through holes (7, 8, 9, 10, 11) communicating with a respective channel (5, 6);
a first channel (5) connecting two or more of said through holes (7, 8, 9);
the second channel (6) connecting two or more other through holes (10, 11);
through holes first (9) and second (10), respectively connected to said channels first (5) and second (6), coinciding with a suction port and with a delivery port, respectively, of a micropump module (P) fixed onto the silicon platform (1);
at least the through hole (9) coinciding with the suction port of the micropump (P) being connected through said first channel (5) to a through hole (7) coinciding with the outlet port of a first solvent release microvalve module (V1) from a first supply cartridge (C1) and to a through hole (8) coinciding with the outlet port of a second oxidable compound release microvalve module (V2) from a second supply cartridge (C2);
upon coupling the channelled (5, 6) bottom side of said silicon platform (1) to said flat coupling area of the device (FC), an inlet of said solution feed manifold (3) coinciding with said second channel (6).
The depleted solution discharge manifold (4) of the device (FC) has an outlet connecting to the first channel (5) of the silicon flow connector (1) and through a fifth through hole (11) coinciding with the inlet of a third solution discharge microvalve module (V3), to a third cartridge (C3) into which bleeding depleted waste solution.

Abstract translation: 对于通过该微流体系统中的可氧化的化合物的至少一个溶液的流连接器被供给到进料歧管中的能量转换具有与流连接器的平坦耦合区域电化学装置（FC）的（3）是由作为一个独特的文章 的制造适用走上电化学装置。 流连接器包括（1）具有至少两个不同的信道的单晶硅平台（5，6）限定在所述平台的底侧，在其上的顶侧的功能模块（P，C1，C2，C3一个多元化 ，V1，V2，V3）所述微流体系统的的通孔（7，8，9，10固定在respectivement的对应关系，11）与一个respectivement通道（5连通，6）; 连接两个或通孔多个所述第一信道（5）（7，8，9）; 连接两个或多个其它通孔（10，11）的第二通道（6）; 通过第一（9）和第二（10），分别连接到所述通道的孔的第一（5）和第二（6），分别与吸入口和一个排出口重合，一个微型泵模块（P）的，固定在 硅平台（1）; 至少所述通孔（9）与所述微型泵的吸入口（P）通过所述第一通道（5）被连接到一个通孔重合（7）与第一溶剂释放微阀模块的出口（V1）一致 从第一供应盒（C1）和一个通孔（8）与来自第二供给筒（C2）的第二可氧化的化合物释放微型阀模块（V2）的出口重合; 在所述引导联接（5,6）所述硅平台（1）到所述装置（FC）的所述平耦合区的底侧到所述入口进料溶液歧管（3）与所述第二（6）信道重合。 该贫化的溶液排出歧管（4）的装置（FC）的具有出口连接到所述第一通道（5）的硅流连接器（1），并通过第五通孔（11）与第三溶液的入口重合 微排出阀模块（V3），在第三盒（C3）到其中出血耗尽废溶液。

公开(公告)号：EP1696485A1

公开(公告)日：2006-08-30

申请号：EP05425096.4

申请日：2005-02-24

Applicant: STMicroelectronics S.r.l.

Inventor： Leonardi, Salvatore ,  Modica, Roberto

IPC: H01L23/544 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/8232 ,  H01L21/8238 ,  H01L21/316

CPC classification number: H01L23/544 ,  H01L21/32 ,  H01L21/76286 ,  H01L21/8222 ,  H01L21/823481 ,  H01L21/823878 ,  H01L21/8249 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/7824 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: Process for manufacturing an electronic semiconductor device, wherein a SOI wafer (20) is provided, formed by a bottom layer (21) of semiconductor material, an insulating layer (22), and a top layer (50) of semiconductor material, stacked on top of one another; alignment marks (32) are formed in the top layer; an implanted buried region (30) is formed, aligned to the alignment marks; a hard mask (52,53) is formed on top of the top layer (23;50) so as to align it to the alignment marks (32); using the hard mask, the top layer (23;50) is selectively removed so as to form a trench (55) extending up to the insulating layer (22); there a lateral-insulation region (60) in the trench (55), that is contiguous to the insulating layer (22) and delimits with the latter an insulated well (61) of semiconductor material; and electronic components (65-76) are formed in the top layer (23;50).

Abstract translation: 用于制造电子半导体器件，worin一个SOI晶片（20）的过程被提供，由半导体材料的上绝缘层（22）的底层（21），和半导体材料的顶层（50），层叠形成 彼此的顶部上; 对准标记（32）形成在所述顶层; 注入掩埋区（30）形成，对准的对准标记; 硬掩模（52,53）形成在所述顶层（23; 50）的顶部上，以便将其对准的对准标记（32）; 使用硬掩模，顶部层（23; 50）被选择性地去除以形成沟槽（55）一直延伸到绝缘层（22）; 在（55）有一横向绝缘区域（60）的沟槽所做的是邻接于绝缘层（22），并用绝缘良好的（61）的半导体材料的后界定; 和电子部件（65-76）形成在所述顶层（23; 50）。

公开(公告)号：EP0966042A1

公开(公告)日：1999-12-22

申请号：EP98830373.1

申请日：1998-06-19

Applicant: STMicroelectronics S.r.l.

Inventor： Leonardi, Salvatore

IPC: H01L27/07 ,  H01L27/06

CPC classification number: H01L27/0716 ,  H01L27/0635 ,  H01L29/7302 ,  H01L29/739 ,  H01L29/7803 ,  H01L29/7808

Abstract: This invention relates to a monolithic integrated device with protection structure, formed in a semiconductor material substrate (1) having a first conductivity type, which device comprises at least a first epitaxial layer (2) formed on the substrate (1) and having the same conductivity type of the substrate.
The integrated device further comprises a first transistor (T1) of the bipolar type formed of a base region (3,4,5) having a second conductivity type and including a first buried region (3) formed in the first epitaxial layer (2), and having a first diffused region (4) which extends from the first buried region (3) to contact a top surface of the integrated device 20 through a surface contact region (5) with a high concentration of dopant material.
Said first transistor (T1) also has an emitter region (6,7) with the first conductivity type, embedded in the base region (3,4,5), and including a second buried region (6) formed on the first buried region (3) and a second diffused region (7), with a high concentration of dopant material, which extends from the second buried region (6) to contact the top surface of the integrated device.
The integrated device additionally comprises a second transistor (M1) of the MOS type having a drain region (6,7) formed in the emitter region (6,7) of the first transistor (T1), said drain region (6,7) incorporating a third diffused region (10) with a high concentration of dopant material and the first conductivity type which includes a source region of the second transistor (M1).
Said integrated device is characterized in that the protection structure (12) is formed of the overlap of the surface contact region (5) and at least one of the diffused regions (7,10) with a high concentration of dopant material to provide a low breakdown voltage junction of the Zener type.
Alternatively, instead of the second transistor M1 of the MOS type, the integrated device may comprise a second transistor (T2) of the bipolar type having a collector region (6,7) formed within the emitter region of the first bipolar transistor (T1), said collector region (6,7) having, embedded therein, a third diffused region (10) with a high concentration of a dopant material and the first conductivity type, which includes an emitter region of the second transistor (T2).

Abstract translation: 本发明涉及一种具有保护结构的单片集成器件，其形成在具有第一导电类型的半导体材料衬底（1）中，该器件至少包括形成于衬底（1）上的第一外延层（2） 基板的导电类型。 集成器件还包括由具有第二导电类型的基极区（3,4,5）形成的双极型的第一晶体管（T1），并且包括形成在第一外延层（2）中的第一掩埋区（3） 并且具有从第一掩埋区域（3）延伸的第一扩散区域（4），以通过具有高浓度掺杂剂材料的表面接触区域（5）接触集成器件20的顶表面。 所述第一晶体管（T1）还具有嵌入基极区（3,4,5）中的具有第一导电类型的发射极区（6,7），并且包括形成在第一掩埋区 （3）和具有高浓度的掺杂剂材料的第二扩散区域（7），其从第二掩埋区域（6）延伸以与集成器件的顶表面接触。 集成器件还包括MOS型的第二晶体管（M1），其具有形成在第一晶体管（T1）的发射极区域（6,7）中的漏极区域（6,7），所述漏极区域（6,7） 结合具有高浓度掺杂剂材料的第三扩散区域（10）和包括第二晶体管（M1）的源极区域的第一导电类型。 所述集成器件的特征在于，保护结构（12）由表面接触区域（5）和至少一个扩散区域（7,10）与高浓度掺杂剂材料的重叠形成，以提供低的 齐纳二极管的击穿电压接点。 或者，代替MOS型的第二晶体管M1，集成器件可以包括双极型的第二晶体管（T2），其具有形成在第一双极晶体管（T1）的发射极区域内的集电极区域（6,7） 所述集电极区域（6,7）嵌入其中具有掺杂剂材料的高浓度的第三扩散区域（10）和包括第二晶体管（T2）的发射极区域的第一导电类型。