公开(公告)号：EP1003155A1

公开(公告)日：2000-05-24

申请号：EP99309211.3

申请日：1999-11-18

Applicant: STMicroelectronics, Inc.

Inventor： Patti, Giuseppe ,  Lee, Eugene C. ,  Alini, Roberto

IPC: G11B5/012 ,  G11B20/24 ,  G11B20/10

CPC classification number: G11B5/012 ,  G11B2005/0016

Abstract: To reduce thermal interference in the read signal of a disk drive, a variable or programmable resistance is used to change the transfer function of a filter (112) in the read channel of the disk drive to filter the read signal. The filter has a first cut-off frequency related to the programmed resistance during normal operation of the disk drive. When thermal interference is detected in the read signal, the resistance is programmed to another value resulting in the filter having a second cut-off frequency. The resistance element is variable or programmable to different values resulting in one of a multitude of cut-off frequencies for the filter.

Abstract translation: 为了减少在磁盘驱动器的读信号的热干扰，可变的或可编程的电阻被用来改变在盘驱动器的读通道的过滤器（112）的传递函数来过滤的读取信号。 该过滤器具有磁盘驱动器的正常手术期间相关的编程电阻的第一截止频率。 当在所读取的信号中检测到热干扰，电阻被编程为anotherValue导致过滤器具有第二截止频率。 电阻元件是可变的或可编程的，以在截止频率为所述过滤器的多个中的一个所得到的不同的值。

公开(公告)号：EP1585130A2

公开(公告)日：2005-10-12

申请号：EP05251685.3

申请日：2005-03-18

Applicant: STMicroelectronics, Inc.

Inventor： Ozanoglu, Kemal ,  Posat, Baris ,  Alini, Roberto

IPC: G11B20/10

CPC classification number: G11B20/10009 ,  G11B20/22 ,  G11B2005/0016

Abstract: A preamplifier for correcting for thermal asperity transients in disk drives using magneto resistive read heads. The preamplifier has an input gain stage receiving a signal from the read head and an output buffer outputting a reader output to a read channel that is filtered of thermal asperity transients by a high pass filter positioned between the input gain stage and the output buffer. The high pass filter is voltage controlled based on an input control signal from a filter controller. The filter controller uses a low pass filter functioning as a peak detector to detect peaks in either the input or output voltage of the high pass filter. The low pass filter output is applied to a non-linear function generator generating the control signal for the high pass filter based on an increasing function of the absolute value of the low pass filter output.

Abstract translation: 一种前置放大器，用于使用磁阻读取头校正磁盘驱动器中的热凹凸瞬变。 前置放大器具有接收来自读取头的信号的输入增益级和输出缓冲器，该输出缓冲器通过位于输入增益级和输出缓冲器之间的高通滤波器将读出器输出输出输出到读取通道，该读取通道被过滤掉热不平坦瞬变。 高通滤波器基于来自滤波器控制器的输入控制信号进行电压控制。 滤波器控制器使用用作峰值检测器的低通滤波器来检测高通滤波器的输入或输出电压中的峰值。 低通滤波器输出被应用于基于低通滤波器输出的绝对值的增加函数产生高通滤波器的控制信号的非线性函数发生器。

公开(公告)号：EP1083550A2

公开(公告)日：2001-03-14

申请号：EP00307519.9

申请日：2000-08-31

Applicant: STMicroelectronics, Inc.

Inventor： Patti, Giuseppe ,  Alini, Roberto ,  Pakriswamy, Elango

IPC: G11B5/012 ,  G11B5/02

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09

Abstract: A circuit (102,103) for controlling the write head (101) of a magnetic disk storage device includes a pull-up device (104) for selectively providing a current to the write head and a current sink circuit (106) selectively activated to draw current from the write head. A bootstrap circuit (108) is coupled to the current sink circuit. When reversing the direction of current flow through the write head from a first direction to the write head to a second direction from the write head terminal, the bootstrap circuit and the current sink circuit are activated to rapidly draw current from the write head. When the current in the write head nears and/or slightly surpasses the desired destination level, the bootstrap circuit is deactivated.

Abstract translation: 一种用于控制磁盘存储装置的写入头（101）的电路（102,103）包括用于选择性地提供电流，以写头和一个电流吸收电路（106）的上拉设备（104）选择性地激活以汲取电流 从写头。 自举电路（108）被耦合到所述电流宿电路。 倒车时电流流过写入头从第一方向到写入头从写头端的第二方向的方向上，自举电路和所述电流宿电路被激活以快速绘制从写入头的电流。 当在写头的当前接近和/或略优于期望的目的地级，自举电路被停用。

公开(公告)号：EP1083549A2

公开(公告)日：2001-03-14

申请号：EP00307508.2

申请日：2000-08-31

Applicant: STMicroelectronics, Inc.

Inventor： Patti, Giuseppe ,  Alini, Roberto ,  DeNoyer, Gilles P.

IPC: G11B5/012 ,  G11B5/02

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09

Abstract: A circuit for controlling the write head (101) of a magnetic disk storage device includes a pull-up device (104) coupled to a terminal (101a) of the write head, for selectively providing a current to the write head through the terminal, parallel-connected first (106) and second (107) current sink circuits, each coupled to the write head terminal and selectively activated to draw current from the write head. A control circuit (130) individually activates the pull-up device and the first and second current sink circuits to reverse the direction of current flow through the write head. When the current nears the desired current level, the second current sink circuit is deactivated and the pull-up device is immediately activated for a predetermined period of time. Current overshoot and undershoot of the write head current is minimized.

Abstract translation: 用于控制磁盘存储装置的写入头（101）的电路包括耦合到写入头的终端（101a）的上拉装置（104），用于通过终端有选择地向写入头提供电流， 并联连接的第一（106）和第二（107）电流吸收电路，每个耦合到写入头终端并选择性地激活以从写入头抽取电流。 控制电路（130）分别启动上拉装置和第一和第二电流吸收电路以反转通过写入头的电流的方向。 当电流接近期望的电流电平时，第二电流吸收电路被去激活，并且上拉装置立即被激活一段预定的时间。 写头电流的电流过冲和欠冲最小。

公开(公告)号：EP1310955A3

公开(公告)日：2007-02-21

申请号：EP02257758.9

申请日：2002-11-08

Applicant: STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Posat, Baris ,  Ozanoglu, Kemal ,  Alini, Roberto

IPC: G11B19/02 ,  G11B5/012 ,  G11B5/02

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013

Abstract: A circuit and method are disclosed for relatively rapidly causing the current flowing through a write head to transition between steady states without generating an appreciable amount of capacitively-coupled noise. Embodiments of the present invention generally provide drive voltage signals to the write head that have no common mode voltage levels during transitions between steady state current levels in the write head. In other words, the drive voltage signals applied to the write head are substantially entirely differential during write head current transitions. In an exemplary embodiment of the present invention, a driver circuit (100) includes switching circuitry (111,112,113,114,116,117,118,119) connected between the terminals (42A,42B) of the write head (42) and reference voltage supplies, such as positive and negative voltage supplies. The driver circuit further includes timing circuitry (125) that generates control signals for controlling the switching circuitry.

公开(公告)号：EP1585130A3

公开(公告)日：2005-12-14

申请号：EP05251685.3

申请日：2005-03-18

Applicant: STMicroelectronics, Inc.

Inventor： Ozanoglu, Kemal ,  Posat, Baris ,  Alini, Roberto

IPC: G11B20/22

CPC classification number: G11B20/10009 ,  G11B20/22 ,  G11B2005/0016

Abstract: A preamplifier for correcting for thermal asperity transients in disk drives using magneto resistive read heads. The preamplifier has an input gain stage receiving a signal from the read head and an output buffer outputting a reader output to a read channel that is filtered of thermal asperity transients by a high pass filter positioned between the input gain stage and the output buffer. The high pass filter is voltage controlled based on an input control signal from a filter controller. The filter controller uses a low pass filter functioning as a peak detector to detect peaks in either the input or output voltage of the high pass filter. The low pass filter output is applied to a non-linear function generator generating the control signal for the high pass filter based on an increasing function of the absolute value of the low pass filter output.

Abstract translation: 前置放大器，用于校正使用磁阻读取磁头的磁盘驱动器中的热突起瞬变。 前置放大器具有从读取头接收信号的输入增益级以及将读取器输出输出到读取通道的输出缓冲器，所述读取通道由位于输入增益级和输出缓冲器之间的高通滤波器对热异常瞬态进行滤波。 高通滤波器是基于来自滤波器控制器的输入控制信号进行电压控制的。 滤波器控制器使用低通滤波器作为峰值检测器来检测高通滤波器输入或输出电压中的峰值。 基于低通滤波器输出的绝对值的递增函数，将低通滤波器输出应用于产生用于高通滤波器的控制信号的非线性函数发生器。

公开(公告)号：EP1310955A2

公开(公告)日：2003-05-14

申请号：EP02257758.9

申请日：2002-11-08

Applicant: STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Posat, Baris ,  Ozanoglu, Kemal ,  Alini, Roberto

IPC: G11B19/02 ,  G11B5/012 ,  G11B5/02

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013

Abstract: A circuit and method are disclosed for relatively rapidly causing the current flowing through a write head to transition between steady states without generating an appreciable amount of capacitively-coupled noise. Embodiments of the present invention generally provide drive voltage signals to the write head that have no common mode voltage levels during transitions between steady state current levels in the write head. In other words, the drive voltage signals applied to the write head are substantially entirely differential during write head current transitions. In an exemplary embodiment of the present invention, a driver circuit (100) includes switching circuitry (111,112,113,114,116,117,118,119) connected between the terminals (42A,42B) of the write head (42) and reference voltage supplies, such as positive and negative voltage supplies. The driver circuit further includes timing circuitry (125) that generates control signals for controlling the switching circuitry.

Abstract translation: 公开了一种电路和方法，用于相对快速地使流过写入头的电流在稳定状态之间转变而不产生可观量的电容耦合噪声。 本发明的实施例通常在写入头中的稳态电流电平之间的转换期间向写入头提供不具有共模电压电平的驱动电压信号。 换句话说，施加到写入头的驱动电压信号在写入头电流转换期间基本上完全不同。 在本发明的示例性实施例中，驱动器电路（100）包括连接在写入头（42）的端子（42A，42B）之间的开关电路（111,112,113,114,116,117,118,119）和诸如正和负电压源的参考电压源。 驱动器电路还包括产生用于控制开关电路的控制信号的定时电路（125）。

公开(公告)号：EP1083549B1

公开(公告)日：2010-02-17

申请号：EP00307508.2

申请日：2000-08-31

Applicant: STMicroelectronics, Inc.

Inventor： Patti, Giuseppe ,  Alini, Roberto ,  DeNoyer, Gilles P.

IPC: G11B5/012 ,  G11B5/02 ,  G11B5/09

CPC classification number: G11B5/022 ,  G11B5/012 ,  G11B5/02 ,  G11B5/09

公开(公告)号：EP1603120A1

公开(公告)日：2005-12-07

申请号：EP05252821.3

申请日：2005-05-09

Applicant: STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02 ,  G05F3/26

CPC classification number: G11B5/09 ,  G11B2005/0016 ,  H02M3/073

Abstract: A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a current source, such as a MOS transistor, connected to the input node of a capacitor. During the overshoot duration, the current source operates at saturation to generate a pulsed current with an amplitude of half the load current. The circuit includes another transistor in series with the current generator between the capacitor and the driver output. A forward bias diode is connected between the capacitor output node and high voltage reference and enters reverse bias during overshoot duration swinging the driver output voltage above supply voltage.

Abstract translation: 写驱动器通过连接到写头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准电源电压和低电压基准之间的升压电路，并且包括连接到电容器的输入节点的诸如MOS晶体管的电流源。 在过冲持续时间期间，电流源工作在饱和状态，以产生具有一半负载电流幅度的脉冲电流。 该电路包括与电容器和驱动器输出之间的电流发生器串联的另一个晶体管。 正向偏置二极管连接在电容器输出节点和高电压基准之间，并在驱动器输出电压高于电源电压的过冲持续时间内进入反向偏置。

公开(公告)号：EP1587067A3

公开(公告)日：2005-11-02

申请号：EP05252273.7

申请日：2005-04-12

Applicant: STMicroelectronics, Inc.

Inventor： Venca, Alessandro ,  Alini, Roberto ,  Posat, Baris

IPC: G11B5/02 ,  G05F3/26 ,  H04L25/02

CPC classification number: G11B5/02

Abstract: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.