公开(公告)号：US20230014037A1

公开(公告)日：2023-01-19

申请号：US17690154

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euntaek Jung ,  Jaeho Kim ,  Joonsung Kim ,  Jiwon Kim ,  Sukkang Sung ,  Sangdon Lee ,  Jong-Min Lee

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/528 ,  G11C16/04

Abstract: A semiconductor device includes an electrode structure including electrodes stacked on a substrate and an insulating pattern on an uppermost electrode of the electrodes, a vertical structure that penetrates the electrode structure and is connected to the substrate, a first insulating layer on the electrode and the vertical structure, a conductive pattern that penetrates the first insulating layer and is connected to the vertical structure, an upper horizontal electrode on the conductive pattern, and an upper semiconductor pattern that penetrates the upper horizontal electrode and is connected to the conductive pattern. The conductive pattern has a first side surface on the vertical structure and a second side surface on the insulating pattern.

公开(公告)号：US20250120089A1

公开(公告)日：2025-04-10

申请号：US18830677

申请日：2024-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehoon Lee ,  Minyong Lee ,  Junhyoung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B43/40 ,  G11C16/04 ,  H01L23/00 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A nonvolatile memory device includes a peripheral circuit structure including a peripheral circuit, and a lower insulating structure on the peripheral circuit, a cell array structure having a cell area and a peripheral connection area and including an upper insulating structure in contact with the lower insulating structure, a cell stack in the cell area on the upper insulating structure, a common source line layer on the cell stack and having a common source opening, a plurality of cell channel structures extending in a vertical direction in the cell stack and into the common source line layer, and a support structure extending in the vertical direction in the cell stack and into the common source opening, and a pad pattern extending from the peripheral connection area to the cell area on the cell array structure and overlapping the support structure in the vertical direction.

公开(公告)号：US20250081472A1

公开(公告)日：2025-03-06

申请号：US18766970

申请日：2024-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehoon Lee ,  Joonyoung Kwon ,  Junhyoung Kim ,  Sukkang Sung

IPC: H10B80/00 ,  H01L25/065 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A non-volatile memory device includes a substrate, a first semiconductor layer including a memory cell array on the substrate, a second semiconductor layer including a peripheral circuit that is configured to write data to or read the data from the memory cell array, where the second semiconductor layer is on the first semiconductor layer, and a protrusion structure including a wire that extends into at least a portion of the first semiconductor layer and at least a portion of the second semiconductor layer, where the protrusion structure extends from a first surface of the first semiconductor layer and from a first surface of the second semiconductor layer, and where the protrusion structure extends in a second direction that is perpendicular to the first direction.

公开(公告)号：US20250063729A1

公开(公告)日：2025-02-20

申请号：US18666514

申请日：2024-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Joonyoung Kwon ,  Siwan Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B41/35 ,  H01L23/00 ,  H01L25/18 ,  H10B12/00 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a plate layer; conductive layers spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer on the plate layer, extending by different lengths in a second direction perpendicular to the first direction, and forming a staircase region; a gap-fill insulating layer on the staircase region; and vertical structures penetrating through the gap-fill insulating layer and the conductive layers in the staircase region and extending in the first direction, and wherein the gap-fill insulating layer includes voids disposed symmetrically with respect to at least one of the vertical structures or a center of the staircase region in a third direction perpendicular to the first direction and the second direction.

公开(公告)号：US20240371730A1

公开(公告)日：2024-11-07

申请号：US18411171

申请日：2024-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum Lee ,  Woosung Yang ,  Jimo Gu ,  Sukkang Sung

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

Abstract: Disclosed are semiconductor devices and semiconductor packages including the same. The semiconductor package includes a package substrate, and a first chip stack and a second chip stack that are stacked on the package substrate. Each of the first and second chip stacks includes a plurality of vertically stacked semiconductor chips. Each of the semiconductor chips includes a plurality of first vertical connection structures and a plurality of second vertical connection structures. The first vertical connection structures of the semiconductor chips in the second chip stack overlap and are connected with the second vertical connection structures of the semiconductor chips in the first chip stack.

公开(公告)号：US20240312937A1

公开(公告)日：2024-09-19

申请号：US18671649

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Jiwon Kim ,  Jaeho Ahn ,  Joon-Sung Lim ,  Sukkang Sung

IPC: H01L23/00 ,  G11C16/08 ,  G11C16/10 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L24/08 ,  G11C16/08 ,  G11C16/10 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/08135 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device and electronic system, the device including a cell structure stacked on a peripheral circuit structure, wherein the cell structure includes a first interlayer dielectric layer and first metal pads exposed at the first interlayer dielectric layer and connected to gate electrode layers and channel regions, the peripheral circuit structure includes a second interlayer dielectric layer and second metal pads exposed at the second interlayer dielectric layer and connected to a transistor, the first metal pads include adjacent first and second sub-pads, the second metal pads include adjacent third and fourth sub-pads, the first and third sub-pads are coupled, and a width of the first sub-pad is greater than that of the third sub-pad, and the second sub-pad and the fourth sub-pad are coupled, and a width of the fourth sub-pad is greater than that of the second sub-pad.

公开(公告)号：US20240079323A1

公开(公告)日：2024-03-07

申请号：US18350999

申请日：2023-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung Kwon ,  Dawoon Jeong ,  Jiyoung Kim ,  Sukkang Sung ,  Woosung Yang

IPC: H01L23/528 ,  G11C5/06 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H01L23/5283 ,  G11C5/063 ,  H01L25/0655 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a first conductive plate structure and a second conductive plate structure, arranged at a same vertical level on a semiconductor chip and horizontally spaced apart from each other on the semiconductor chip, a first structure on the first conductive plate structure and including first separation structures and first memory blocks, and a second structure on the second conductive plate structure and including second separation structures and second memory blocks. The first memory blocks are spaced apart from each other by the first separation structures, and extend in parallel to each other in a first horizontal direction. The second memory blocks are spaced apart from each other by the second separation structures, and extend in parallel to each other in a second horizontal direction. The first and second horizontal directions are parallel to an upper surface of the first conductive plate structure, and are perpendicular to each other.

公开(公告)号：US11715684B2

公开(公告)日：2023-08-01

申请号：US17376240

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin Hwang ,  Jiwon Kim ,  Jaeho Ahn ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L27/115 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B43/27

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L24/20 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/2105 ,  H01L2224/24146 ,  H01L2924/1431 ,  H01L2924/14511 ,  H10B43/27

Abstract: A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel.

公开(公告)号：US20220173060A1

公开(公告)日：2022-06-02

申请号：US17470644

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A nonvolatile memory device and a data storage system including the same are provided. The nonvolatile memory device includes: a first structure including at least one first memory plane; and a second structure bonded to the first structure and including at least one second memory plane, wherein the number of the at least one first memory plane included in the first structure is different from the number of the at least one second memory plane included in the second structure.

公开(公告)号：US20220157838A1

公开(公告)日：2022-05-19

申请号：US17467568

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device and a data storage system including the same, the semiconductor device including: a first structure including a peripheral circuit; and a second structure, including: a pattern structure; an upper insulating layer; a stack structure between the first structure and the pattern structure and including first and second stack portions spaced apart from each other, the first and second stack portions respectively including horizontal conductive layers and interlayer insulating layers alternately stacked; separation structures penetrating through the stack structure; memory vertical structures penetrating through the first stack portion; and a contact structure penetrating through the second stack portion, the pattern structure, and the upper insulating layer, wherein the contact structure includes a lower contact plug penetrating through at least the second stack portion and an upper contact plug contacting the lower contact plug and extending upwardly to penetrate through the pattern structure and the upper insulating layer.