公开(公告)号：US12217800B2

公开(公告)日：2025-02-04

申请号：US18591728

申请日：2024-02-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.

公开(公告)号：US12160992B2

公开(公告)日：2024-12-03

申请号：US17563547

申请日：2021-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoung Kim ,  Bumkyu Kang ,  Joonsung Lim ,  Sukkang Sung

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a substrate having a cell region and a connection region, a first stack structure with a plurality of first gate layers and a plurality of first interlayer insulating layers, and a second stack structure with a plurality of second gate layers and a plurality of second interlayer insulating layers. Each of the first gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. Each of the second gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. A thickness difference between the end and central portions of each first gate layer is different from a thickness difference between the end and central portions of each second gate layer.

公开(公告)号：US20240249775A1

公开(公告)日：2024-07-25

申请号：US18591728

申请日：2024-02-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeho Ahn ,  Jiwon Kim ,  Sungmin Hwang ,  Joonsung Lim ,  Sukkang Sung

IPC: G11C16/10 ,  G11C16/26 ,  H01L23/48 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/10 ,  G11C16/26 ,  H01L23/481 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor memory device includes: a semiconductor substrate having a first surface and a second surface opposing each other; a back-side insulating layer below the second surface of the semiconductor substrate; an external input/output conductive pattern below the back-side insulating layer; a circuit device including a gate electrode and a source/drain region, on the first surface of the semiconductor substrate; an internal input/output conductive pattern on the first surface of the semiconductor substrate, the internal input/output conductive pattern having at least a portion disposed on the same level as at least a portion of the gate electrode; a through-electrode structure penetrating through the semiconductor substrate and the back-side insulating layer and electrically connected to the internal input/output conductive pattern and the external input/output conductive pattern; and a memory cell array region disposed on a level higher than the circuit device, on the first surface of the semiconductor substrate.

公开(公告)号：US20220399368A1

公开(公告)日：2022-12-15

申请号：US17701304

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Sangdon Lee ,  Sungmin Hwang ,  Sukkang Sung

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/48

Abstract: A semiconductor device includes a stack structure, first separation patterns passing through the stack structure, a second separation pattern passing through at least a portion of the stack structure between the first separation patterns, and a cutting channel structure passing through the stack structure and having an end portion partially cut by the second separation pattern. A channel layer of the cutting channel structure has a ring shape cut by the second separation pattern to have end portions of the channel layer which are spaced apart from each other.

公开(公告)号：US20250120080A1

公开(公告)日：2025-04-10

申请号：US18666888

申请日：2024-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Bumkyu Kang ,  Sehoon Lee ,  Sukkang Sung

IPC: H10B43/27 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes a first substrate structure, and a second substrate structure connected to the first substrate structure and including circuit elements and second bonding metal layers. The first substrate structure includes gate electrodes stacked along a first direction, a supporter layer on the gate electrodes, channel structures extending along the first direction while penetrating the gate electrodes, separation regions extending in the first direction and a second direction by penetrating through the gate electrodes, and first bonding metal layers connected to the second bonding metal layers. The separation regions respectively include first regions spaced apart from each other along the second direction and a second region surrounding side surfaces of the first regions and extending in the second direction. The first regions and the channel structures penetrate the supporter layer, and a portion of a lower surface of the supporter layer is in contact with the second region.

公开(公告)号：US20240194266A1

公开(公告)日：2024-06-13

申请号：US18518496

申请日：2023-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Jiyoung Kim ,  Woosung Yang ,  Dohyung Kim ,  Sukkang Sung

IPC: G11C16/08 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: G11C16/08 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a first substrate structure including a first decoder circuit region, a second decoder circuit region, and a page buffer circuit region, and a second substrate structure connected to the first substrate structure. The second substrate structure includes a first cell structure that includes first horizontally extending gate electrodes, and a second cell structure that includes second horizontally extending gate electrodes. The second cell structure is disposed below the first cell structure. A first stair structure is disposed to one side of the first and second cell structures, and a second stair structure is disposed to a second side opposite the first side. a dummy structure is disposed below the first stair structure. First contact plugs pass through the first stair structure and the first dummy structure and are respectively connected to the first gate electrodes, and second contact plugs pass through the second stair structure and are respectively connected to the second gate electrodes.

公开(公告)号：US20240107767A1

公开(公告)日：2024-03-28

申请号：US18463620

申请日：2023-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Joonyoung Kwon ,  Jiyoung Kim ,  Jinhyuk Kim ,  Sukkang Sung

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A semiconductor device includes a gate electrode structure, a first division pattern, and a memory channel structure. The gate electrode structure includes gate electrodes stacked in a first direction and extending in a second direction. The first division pattern extends in the second direction through the gate electrode structure, and divides the gate electrode structure in a third direction. The memory channel structure extends through the gate electrode structure, and includes a channel and a charge storage structure. The first division pattern includes first and second sidewalls opposite to each other in the third direction. First recesses are spaced apart from each other in the second direction on the first sidewall, and second recesses are spaced apart from each other in the second direction on the second sidewall. The first and second recesses do not overlap in the third direction.

公开(公告)号：US20240099012A1

公开(公告)日：2024-03-21

申请号：US18308222

申请日：2023-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung Kwon ,  Jiyoung Kim ,  Junhyoung Kim ,  Sukkang Sung

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B80/00

CPC classification number: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B80/00

Abstract: A semiconductor device includes a peripheral circuit structure including a plurality of circuit areas, a cell array structure including a pair of memory cell blocks overlapping the peripheral circuit structure in a first direction and spaced apart in a second direction, perpendicular to the first direction, with a peripheral circuit connection area therebetween, a first circuit area of the plurality of circuit areas that overlaps the peripheral circuit connection area in the first direction, and at least one contact plug extending in the first direction from the peripheral circuit connection area, and including a first end portion configured to connect to at least one circuit included in the first circuit area and facing the first circuit area and a second end portion configured to connect to an external connection terminal.

公开(公告)号：US20240055380A1

公开(公告)日：2024-02-15

申请号：US18231838

申请日：2023-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbum KIM ,  Cheonan Lee ,  Sukkang Sung

IPC: H01L23/00 ,  H01L25/065 ,  H10B43/35 ,  H10B41/35

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H10B43/35 ,  H10B41/35 ,  H10B80/00

Abstract: A semiconductor device includes: a first structure including a first substrate and a peripheral circuit disposed on the first substrate; and a second structure including a common source plate and a cell stack disposed on the common source plate and including a plurality of gate electrodes and channel structures, wherein the cell stack includes a plurality of cell blocks including a plurality of main blocks and at least one dummy block disposed at one side of the plurality of main blocks, wherein the common source plate includes a main common source line region and a dummy common source line region, wherein the main common source line region overlaps the plurality of main blocks, and the dummy common source line region is separated from the main common source line region and overlaps the at least one dummy block by being electrically isolated from the at least one dummy block.

公开(公告)号：US20240046994A1

公开(公告)日：2024-02-08

申请号：US18120244

申请日：2023-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheonan LEE ,  Kiwhan Song ,  Gyosoo Choo ,  Sukkang Sung

IPC: G11C16/14 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: G11C16/14 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: The present disclosure provides serial-gate transistors and nonvolatile memory devices including serial-gate transistors. In some embodiments, a nonvolatile memory device includes a plurality of memory blocks, a plurality of pass transistor blocks, and a plurality of gates sequentially arranged in a horizontal direction in a gate region above a semiconductor substrate. Each of the plurality of pass transistor blocks includes a plurality of serial-gate transistors configured to transfer a plurality of driving signals to a corresponding memory block of the plurality of memory blocks. Each of the plurality of serial-gate transistors includes a first source-drain region, a gate region, and a second source-drain region that are sequentially arranged in a horizontal direction at a semiconductor substrate. The plurality of gates are electrically decoupled from each other. A plurality of block selection signals respectively applied to the plurality of gates are controlled independently of each other.