Passive radar receiver system
    22.
    发明授权

    公开(公告)号:US11933873B2

    公开(公告)日:2024-03-19

    申请号:US17696338

    申请日:2022-03-16

    CPC classification number: G01S1/045 G01S19/254 G01S19/30

    Abstract: One example includes a passive radar receiver system including an RF receiver front-end to receive a wireless source signal and a reflected signal. An antenna switch of the front-end switches a first antenna to a receiver chain during a first time to generate first radar signal data based on a combined wireless signal comprising wireless source signal and the reflected signal, and switches a second antenna to the receiver chain during a second time to generate second radar signal data based on the combined wireless signal. A signal processor generates source signal data associated with the wireless source signal based on the first and second radar signal data and generates reflected signal data associated with the reflected signal based on the first and second radar signal data, and generates target radar data associated with a target based on the source and reflected radar signal data.

    Buffer sample size control for variable chirp radar

    公开(公告)号:US10281562B2

    公开(公告)日:2019-05-07

    申请号:US15701252

    申请日:2017-09-11

    Abstract: A method of radar signal processing includes providing an analog front end (AFE) including an amplifier coupled between an antenna and an ADC in a receive path, where an ADC output is coupled to an input of an elastic ADC buffer (elastic buffer) including a divided memory with for writing samples from the ADC (samples) while reading earlier written samples to a first signal processor by a high speed interface. A transmit path includes at least one power amplifier provided by the AFE coupled to drive an antenna. A Greatest Common Divisor (GCD) is determined across all chirps in a radar frame programmed to be used. For each frame a sample size for the elastic buffer is dynamically controlled constant to be equal to the GCD for reading samples from one memory block and writing samples to another memory block throughout all chirps in the frame.

    Range resolution in FMCW radars
    26.
    发明授权

    公开(公告)号:US10094920B2

    公开(公告)日:2018-10-09

    申请号:US14470414

    申请日:2014-08-27

    Abstract: The disclosure provides a radar apparatus for estimating a range of an obstacle. The radar apparatus includes a local oscillator that generates a first ramp segment and a second ramp segment. The first ramp segment and the second ramp segment each includes a start frequency, a first frequency and a second frequency. The first frequency of the second ramp segment is equal to or greater than the second frequency of the first ramp segment when a slope of the first ramp segment and a slope of the second ramp segment are equal and positive. The first frequency of the second ramp segment is equal to or less than the second frequency of the first ramp segment when the slope of the first ramp segment and the slope of the second ramp segment are equal and negative.

    Buffer sample size control for variable chirp radar

    公开(公告)号:US09759808B2

    公开(公告)日:2017-09-12

    申请号:US14939703

    申请日:2015-11-12

    CPC classification number: G01S7/352 G01S7/285 G01S13/282 G01S13/343 G01S13/931

    Abstract: A method of radar signal processing includes providing an analog front end (AFE) including an amplifier coupled between an antenna and an ADC in a receive path, where an ADC output is coupled to an input of an elastic ADC buffer (elastic buffer) including a divided memory with for writing samples from the ADC (samples) while reading earlier written samples to a first signal processor by a high speed interface. A transmit path includes at least one power amplifier provided by the AFE coupled to drive an antenna. A Greatest Common Divisor (GCD) is determined across all chirps in a radar frame programmed to be used. For each frame a sample size for the elastic buffer is dynamically controlled constant to be equal to the GCD for reading samples from one memory block and writing samples to another memory block throughout all chirps in the frame.

    LOOPBACK TECHNIQUES FOR SYNCHRONIZATION OF OSCILLATOR SIGNAL IN RADAR
    30.
    发明申请
    LOOPBACK TECHNIQUES FOR SYNCHRONIZATION OF OSCILLATOR SIGNAL IN RADAR 有权
    用于雷达振荡器信号同步的环回技术

    公开(公告)号:US20170023663A1

    公开(公告)日:2017-01-26

    申请号:US14503181

    申请日:2014-09-30

    Abstract: The disclosure provides a radar apparatus for estimating a position and a velocity of a plurality of obstacles. The radar apparatus includes a slave radar chip. A master radar chip is coupled to the slave radar chip. The master radar chip includes a local oscillator that generates a transmit signal. The slave radar chip receives the transmit signal on a first path and sends the transmit signal back to the master radar chip on a second path. A delay detect circuit is coupled to the local oscillator and receives the transmit signal from the slave radar chip on the second path and the transmit signal from the local oscillator. The delay detect circuit estimates a routing delay from the transmit signal received from the slave radar chip on the second path and from the transmit signal received from the local oscillator.

    Abstract translation: 本公开提供了一种用于估计多个障碍物的位置和速度的雷达装置。 雷达装置包括从属雷达芯片。 主雷达芯片耦合到从属雷达芯片。 主雷达芯片包括产生发射信号的本地振荡器。 从属雷达芯片在第一路径上接收发射信号,并将发射信号发送回第二路径上的主雷达芯片。 延迟检测电路耦合到本地振荡器,并从第二路径上的从属雷达芯片接收发射信号和来自本地振荡器的发射信号。 延迟检测电路从从第二路径上的从雷达芯片接收的发送信号和从本地振荡器接收的发送信号估计路由延迟。

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