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公开(公告)号：US20240183968A1
公开(公告)日：2024-06-06
申请号：US18459116
申请日：2023-08-31
Applicant: Texas Instruments Incorporated
Inventor： Sandeep Rao , Karthik Subburaj , Karthik Ramasubramanian
CPC classification number: G01S13/584 , G01S7/352 , G01S2013/0254
Abstract: In described examples, a frequency modulated continuous wave (FMCW) radar system comprises a first FMCW device that includes a first processor and a second FMCW device that includes a second processor. The first and second processors respectively receive first and second set of FMCW signals corresponding to a field of view (FOV), and—independently from each other—process the first and second sets of FMCW signals to respectively generate first and second sets of virtual antenna array signals. The second FMCW device transmits the second set of virtual antenna array signals to the first FMCW device. The first processor determines angle of arrival information with respect to one or more objects in the FOV in response to the first and second sets of virtual antenna array signals.
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公开(公告)号：US11927689B2
公开(公告)日：2024-03-12
申请号：US17351750
申请日：2021-06-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sujaata Ramalingam , Karthik Subburaj , Pankaj Gupta , Anil Varghese Mani , Karthik Ramasubramanian , Indu Prathapan
IPC: G01S7/292 , G01S7/40 , G01S13/524
CPC classification number: G01S7/2922 , G01S7/4004 , G01S13/5246
Abstract: A system includes a shift register to store data samples, where the shift register includes a cell under test (CUT), a left guard cell, a right guard cell, a left window, and a right window. The system includes two sets of comparators to compare incoming data samples with data samples in the left window and the right window to compute ranks of the incoming data samples. The system includes a sorted index array to store a rank of the data samples in the shift register. The system includes a selector to select a Kth smallest index from the sorted index array and its corresponding data sample from the shift register. The system includes a target comparator, where the first comparator input receives a data sample from the CUT and the second comparator input receives a Kth smallest data sample, and the comparator output indicates a CFAR target detection.
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公开(公告)号：US20230305132A1
公开(公告)日：2023-09-28
申请号：US17948227
申请日：2022-09-20
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Kameswaran Vengattaramane , Shankar Ram Narayana Moorthy , Vashishth Dudhia
CPC classification number: G01S13/38 , G01S7/356 , G01S7/4008
Abstract: In described examples, a frequency modulated continuous wave (FMCW) radar system includes an FMCW signal generator, a number N transmitters, N phase shifters, multiple receivers, and a processor. The FMCW signal generator is configured to generate FMCW chirps. Different ones of the phase shifters have different respective base phase shifts selected in response to N. The transmitter is configured to transmit the phase shifted FMCW chirps. The receivers are configured to receive an FMCW chirp reflected by an object in range of the FMCW radar system. The processor is configured to determine a location of the object in range in response to the received FMCW chirp.
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公开(公告)号：USRE49571E1
公开(公告)日：2023-07-04
申请号：US17154611
申请日：2021-01-21
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Sreekiran Samala , Raghu Ganesan
CPC classification number: G01R29/26 , G01S7/03 , G01S7/4008 , G01S7/4017 , G01S13/343 , G01S13/345 , G01S13/931 , H03L7/06
Abstract: A method of measuring phase noise (PN). A PLL frequency synthesizer is provided including a first phase frequency detector (PFD) receiving a reference frequency signal coupled to a first charge pump (CP) coupled to a VCO having an output fedback to the first PFD through a feedback divider that provides a divided frequency signal to the first PFD which outputs an error signal, and PN measurement circuitry including a replica CP coupled to an output of a second PFD or the first PFD. The error signal is received at the replica CP or the divided and reference frequency signal are received at the second PFD, wherein the replica CP outputs a scaled phase error current which is current-to-voltage converted and amplified to provide an amplified phase error voltage, and digitized to provide a digital phase error signal. The digital phase error signal is frequency analyzed to generate a PN measurement.
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公开(公告)号：US20230204717A1
公开(公告)日：2023-06-29
申请号：US17862738
申请日：2022-07-12
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Shankar Narayanamoorthy , Karthik Ramasubramanian , Anand Gadiyar , Dheeraj Kumar Shetty , Shailesh Joshi
IPC: G01S7/40
CPC classification number: G01S7/40 , G01S7/4021 , G01S7/4008
Abstract: Methods, apparatus, systems and articles of manufacture to compensate radar system calibration are disclosed. A radio-frequency (RF) subsystem having a transmit channel, a receive channel, and a loopback path comprising at least a portion of the transmit channel and at least a portion of the receive channel, a loopback measurer to measure a first loopback response of the RF subsystem for a first calibration configuration of the RF subsystem, and to measure a second loopback response of the RF subsystem for a second calibration configuration of the RF subsystem, and a compensator to adjust at least one of a transmit programmable shifter or a digital front end based on a difference between the first loopback response and the second loopback response to compensate for a loopback response change when the RF subsystem is changed from the first calibration configuration to the second calibration configuration.
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Patent Agency Ranking
26.发明申请公开(公告)号：US20220342036A1
公开(公告)日：2022-10-27
申请号：US17856109
申请日：2022-07-01
Applicant: Texas Instruments Incorporated
Inventor： Sandeep Rao , Karthik Subburaj , Dan Wang , Adeel Ahmad
Abstract: In accordance with described examples, a method determines if a velocity of an object detected by a radar is greater than a maximum velocity by receiving on a plurality of receivers at least one frame of chirps transmitted by at least two transmitters and reflected off of the object. A velocity induced phase shift (φd) in a virtual array vector S of signals received by each receiver corresponding to a sequence of chirps (frame) transmitted by each transmitter is estimated. Phases of each element of virtual array vector S are corrected using φd to generate a corrected virtual array vector Sc. A first Fourier transform is performed on the corrected virtual array vector Sc to generate a corrected virtual array spectrum to detect a signature that indicates that the object has an absolute velocity greater than a maximum velocity.
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公开(公告)号：US20220206133A1
公开(公告)日：2022-06-30
申请号：US17138549
申请日：2020-12-30
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Sreekiran Samala , Indu Prathapan
Abstract: In described examples, a frequency modulated continuous wave (FMCW) synthesizer includes a control engine, and a phase locked loop (PLL) including a frequency divider, a control voltage generator (CVG), and a voltage controlled oscillator (VCO). The frequency divider modifies a VCO output frequency based on a control input. The CVG generates a control voltage based on a frequency reference and the frequency divider output. The VCO outputs a FMCW output having the VCO output frequency in response to the control voltage. The control engine generates the control input so that the VCO output frequency: from a first time to a second time, is a first frequency; from the second time to a third time, changes at a first rate; from the third time to a fourth time, changes at a second rate different from the first rate; and from the fourth time to a fifth time, is a second frequency.
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公开(公告)号：US11162986B2
公开(公告)日：2021-11-02
申请号：US16597612
申请日：2019-10-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Tom Altus , Karthik Subburaj , Sreekiran Samala , Raghu Ganesan
Abstract: A method of frequency estimation. A clock output from a frequency synthesizer is received at an input of a ring encoder. The ring encoder generates outputs including a ring encoder output clock and an encoded output which represents LSBs of a clock cycle count of the clock output. A binary counter is run using the ring encoder output clock which provides an output count which represents MSBs of the clock cycle count. Using a reference clock, the encoded output is sampled to provide a sampled encoded output and the output count is sampled to provide a sampled output count. Error correcting is applied to the sampled encoded output to provide a corrected sampled encoded output. The corrected sampled encoded output and sampled output count are combined to provide a combined output which is used for estimating an instantaneous or average frequency of the clock output.
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公开(公告)号：US20210333357A1
公开(公告)日：2021-10-28
申请号：US17368319
申请日：2021-07-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Karthik Subburaj , Karthik Ramasubramanian
IPC: G01S7/35 , G01S7/40 , G01S13/931
Abstract: A radar system is provided that includes a receive channel configured to receive a reflected signal and to generate a first digital intermediate frequency (IF) signal based on the reflected signal, a reference receive channel configured to receive a reflected signal and to generate a second digital IF signal based on the reflected signal, and digital mismatch compensation circuitry coupled to receive the first digital IF signal and the second digital IF signal, the digital mismatch compensation circuitry configured to process the first digital IF signal and the second digital IF signal to compensate for mismatches between the receive channel and the reference receive channel.
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公开(公告)号：USRE48613E1
公开(公告)日：2021-06-29
申请号：US16503240
申请日：2019-07-03
Applicant: Texas Instruments Incorporated
Inventor： Karthik Subburaj , Sreekiran Samala , Raghu Ganesan
Abstract: A method of measuring phase noise (PN). A PLL frequency synthesizer is provided including a first phase frequency detector (PFD) receiving a reference frequency signal coupled to a first charge pump (CP) coupled to a VCO having an output fedback to the first PFD through a feedback divider that provides a divided frequency signal to the first PFD which outputs an error signal, and PN measurement circuitry including a replica CP coupled to an output of a second PFD or the first PFD. The error signal is received at the replica CP or the divided and reference frequency signal are received at the second PFD, wherein the replica CP outputs a scaled phase error current which is current-to-voltage converted and amplified to provide an amplified phase error voltage, and digitized to provide a digital phase error signal. The digital phase error signal is frequency analyzed to generate a PN measurement.
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