公开(公告)号：JP2007324298A

公开(公告)日：2007-12-13

申请号：JP2006151512

申请日：2006-05-31

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SEKINE HIDEKATSU ,  KAWAMOTO KENJI ,  SATO JIN

IPC: H05K1/16

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring board that incorporates a capacitor by which processing time can be reduced, while keeping the processing accuracy of a dielectric layer in the method of manufacturing the printed wiring board.
SOLUTION: A wiring layer 21a and a wiring layer 21b are formed on one surface of an insulating substrate 11, and a conductor layer 22 is formed on the other surface thereof so as to manufacture a wiring board midway of a process. Next, a dielectric layer 31 and a conductor layer 25 are formed on the conductor layer 22, and the conductor layer 25 is patterned to form a capacitor upper electrode 25a. Furthermore, the dielectric layer 31 is finished roughly by sand blasting, by using the capacitor upper electrode 25a as a mask so as to form a dielectric 31a. The dielectric 31a is finished by wet blasting to form a dielectric 31b. The conductor layer 24 is patterned to form a capacitor lower electrode 24a, and a wiring board 100 incorporating a capacitor is obtained.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造布线板的方法，该布线板包括可以减少处理时间的电容器，同时在制造印刷线路板的方法中保持电介质层的处理精度。 解决方案：在绝缘基板11的一个表面上形成布线层21a和布线层21b，并且在其另一个表面上形成导体层22，以便在工艺中途制造布线板。 接着，在导体层22上形成介质层31和导体层25，对导体层25进行图案化，形成电容器上部电极25a。 此外，通过使用电容器上电极25a作为掩模，大致通过喷砂完成电介质层31，以便形成电介质31a。 电介质31a通过湿式喷砂完成以形成电介质31b。 导体层24被图案化以形成电容器下电极24a，并且获得并入电容器的布线板100。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007299849A

公开(公告)日：2007-11-15

申请号：JP2006125192

申请日：2006-04-28

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SATO JIN ,  KAWAMOTO KENJI ,  SEKINE HIDEKATSU

IPC: H05K1/16 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing wiring board including a built-in capacitor for improving accuracy of capacitor capacitance by reducing variation in film thickness of a dielectric material, and enabling high dielectric constant and highly sophisticated functions of the dielectric material. SOLUTION: The method for manufacturing wiring board comprises the steps of (1) generating a dielectric material sheet by forming a metal foil as a first conductive layer on a single surface of the dielectric material; (2) patterning a photoresist in the dielectric material side of the dielectric material sheet; (3) forming a dielectric material pattern by patterning the dielectric material by the etching process with the formed photoresist used as a mask and then peeling the photoresist; (4) laminating the dielectric material sheet achieving contact between an insulating resin sheet and a first electrode via a semi-hardened insulating resin sheet on a wiring in the intermediate process of lamination of the wiring board, by forming the first electrode with the conductive paste bridging over the dielectric material pattern and the first conductor layer; and (5) forming a second electrode and a wiring by forming photoresist on the first conductive layer, exposing and developing the photoresist, and then etching the exposed part of the conductor. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：提供一种包括内置电容器的布线板的制造方法，该方法通过减小电介质材料的膜厚变化而提高电容器电容的精度，并能实现高介电常数和高度复杂的功能 介电材料。 解决方案：制造布线板的方法包括以下步骤：（1）通过在介电材料的单个表面上形成作为第一导电层的金属箔来产生电介质材料片; （2）在电介质材料片的电介质材料侧形成光刻胶; （3）通过用形成的光致抗蚀剂作为掩模通过蚀刻工艺图案化介电材料形成电介质材料图案，然后剥离光致抗蚀剂; （4）通过在布线基板的层压的中间工序中通过半硬化绝缘树脂片在绝缘树脂片和第一电极之间实现接触的电介质材料片，通过用导电膏形成第一电极 桥接在电介质材料图案和第一导体层上; 和（5）通过在第一导电层上形成光致抗蚀剂形成第二电极和布线，曝光和显影光致抗蚀剂，然后蚀刻导体的暴露部分。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007088130A

公开(公告)日：2007-04-05

申请号：JP2005273490

申请日：2005-09-21

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SATO JIN ,  KAWAMOTO KENJI ,  SEKINE HIDEKATSU

IPC: H05K1/16 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a laminate capable of accurately manufacturing a capacity element having an excellent handling performance and a large electrostatic capacity, and an electric circuit board with the built-in capacity element using the laminate. SOLUTION: The laminate has a dielectric layer, a first conductor layer formed on one surface of the dielectric layer, and a second conductor layer formed on the other surface of the dielectric layer. The first conductor layer is thinner than the second one in the laminate. The capacity element and a wiring can be manufactured accurately to the electric circuit board by using such a laminate. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够精确地制造具有优异的处理性能和大的静电容量的电容元件的层压体，以及具有使用层压体的内置电容元件的电路板。 解决方案：层压体具有电介质层，形成在电介质层的一个表面上的第一导体层和形成在电介质层的另一个表面上的第二导体层。 第一导体层比层压板中的第二导体层薄。 可以通过使用这种层叠体，将电容元件和布线精确地制造到电路板。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007005593A

公开(公告)日：2007-01-11

申请号：JP2005184559

申请日：2005-06-24

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SEKINE HIDEKATSU ,  KAWAMOTO KENJI ,  SATO JIN

IPC: H05K3/46 ,  H01L23/12

Abstract: PROBLEM TO BE SOLVED: To provide a wiring substrate which can increase a via reliability by solving a problem with an insufficient bonding force between the electrode of a capacitor and a dielectric layer built in the wiring substrate, decrease capacitance variations, and form a resistance or a signal line in the same layer as the dielectric layer; and also to provide a method for manufacturing the wiring substrate.
SOLUTION: A capacitor 10 is formed on one surface of an insulating layer 41, and has such a structure that a patterned dielectric layer 21a is sandwiched by a capacitor lower electrode 11a and a capacitor upper electrode 51a made of a conductive paste. The upper surface of the capacitor lower electrode 11a is on the same plane as the upper surface of the insulating layer 41. A lead electrode 51b for electrically connecting the capacitor upper electrode 51a, the capacitor lower electrode 11a, and a wiring layer 11b is made in the form of a conductor layer 51 made of a conductive paste.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决问题：为了提供一种可以通过解决电容器的电极与内置在布线基板中的电介质层之间的不充分的接合力的问题来提高通孔可靠性的布线基板，降低电容变化和形成 在与电介质层相同的层中的电阻或信号线; 并且还提供一种制造布线基板的方法。 解决方案：电容器10形成在绝缘层41的一个表面上，并且具有图案化电介质层21a被电容器下电极11a和由导电浆料制成的电容器上电极51a夹持的结构。 电容器下电极11a的上表面位于与绝缘层41的上表面相同的平面上。用于电连接电容器上电极51a，电容器下电极11a和布线层11b的引线电极51b 以导电浆料制成的导体层51的形式。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004228190A

公开(公告)日：2004-08-12

申请号：JP2003011957

申请日：2003-01-21

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SATO JIN ,  KAWAMOTO KENJI

IPC: H05K1/16 ,  B32B15/04 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a capacitor element constituent component with a large electrostatic capacity that can be simply incorporated in a printed substrate by using a normal built-up method, and to provide a substrate with a passive element built therein having high reliability improving performance by shortening of connection wiring of an element. SOLUTION: A laminate able to be made a thin capacitor, reduced in the number of dielectrics suitable for being incorporated in an insulating body layer of a multi-layer printed wiring board while securing a necessary electrostatic capacity, is formed on a metal foil. The laminate is buried in the insulating body layer of the printed wiring board by a normal metal foil lamination means, and labor for mounting the passive element on the printed wiring board is eliminated by performing via formation to contrive continuity of the laminate so as to make the capacitor and a laminating process can be eliminated. The substrate with the built-in passive element capable of mounting with a high density can be obtained by the shortening of the wiring length by taking electric connection with a via. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004172530A

公开(公告)日：2004-06-17

申请号：JP2002339123

申请日：2002-11-22

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： KAWAMOTO KENJI ,  SATO JIN

IPC: H01G4/30 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide a capacitor sheet integrated into a board wherein a thin large electrostatic capacity can be obtained and the capacity can be altered easily; to provide an element integrating board integrating the capacitor sheet thereinto.
SOLUTION: In the capacitor sheet, there are used a plurality of laminated dielectric sheets on a single surface of each of which a plurality of blocked inner-layer electrodes are formed and wherein the inner-layer electrode of each dielectric sheet has the portions overlapping with no inner-layer electrodes of its upper-side and lower-side dielectric sheets. Further, in the capacitor sheet, the electric connections among its outermost-layer electrodes and its inner-layer electrodes are performed by through holes similarly to the manufacturing process of a general printed wiring board. The design of the electrostatic capacity of a capacitor element using this capacitor sheet can be altered easily. Also, when these capacitor sheets are laminated as the capacitor layer of a general printed wiring board, the plurality of capacitor elements can be so integrated at the same time into the printed wiring board as to make obtainable a high-performance thin board integrating the elements thereinto.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2012074660A

公开(公告)日：2012-04-12

申请号：JP2010220344

申请日：2010-09-30

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SATO JIN ,  HAYASHI AKIHIRO

IPC: H01L23/12 ,  H01L21/60

CPC classification number: H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package substrate which improves the fluidity of underfill in mounting a semiconductor chip on the semiconductor package substrate and eliminates underfill void, and performs good connection between the semiconductor chip and the semiconductor package substrate, and to provide a method of manufacturing the same.SOLUTION: A light-shielding part 7c of a glass mask 7a arranged so as to be opposed to a surface of an uncured solder resist 7e is arranged at a position corresponding to a solder resist opening 7d of the uncured solder resist 7e. A gray-tone or half-tone part 7b having a light-shielding degree lower than that of the light-shielding part 7c is arranged around a position corresponding to the solder resist opening 7d of the uncured solder resist 7e and at a position corresponding to a part of the uncured solder resist 7e coating a solder connection terminal 7f. The uncured solder resist 7e is exposed and developed via the glass mask 7a to form a semiconductor package substrate A.

Abstract translation: 要解决的问题：提供一种半导体封装基板，其在将半导体芯片安装在半导体封装基板上时提高底部填充物的流动性，并消除底部填充空隙，并且在半导体芯片和半导体封装基板之间进行良好的连接，以及 以提供其制造方法。 解决方案：将与未固化的阻焊剂7e的表面相对配置的玻璃掩模7a的遮光部7c配置在与未固化的阻焊剂7e的阻焊口7d对应的位置。 具有比遮光部7c低的遮光度的灰色调或半色调部7b配置在与未固化阻焊剂7e的阻焊剂开口部7d对应的位置的周围， 未固化的阻焊剂7e的一部分涂覆焊料连接端子7f。 未固化的阻焊剂7e通过玻璃掩模7a曝光和显影，以形成半导体封装基板A.版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2008288298A

公开(公告)日：2008-11-27

申请号：JP2007130170

申请日：2007-05-16

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： AZUMA NAO ,  SATO JIN ,  KAWAMOTO KENJI

IPC: H05K3/46

CPC classification number: H01L2224/04105 ,  H01L2224/19 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/19105 ,  H01L2924/00012

Abstract: PROBLEM TO BE SOLVED: To solve the problem that the thermal control of an active part is difficult and a reliability on the operation of a part is damaged because a base material mounting the active part and a passive part is brought to a semirigid state, a handling property during manufacture is deteriorated since glass cloth is not contained and a conventional wiring board with the built-in part has an adverse effect even on the reliability of a product and the periphery of an electronic part is coated with a resin in the conventional wiring board with the built-in part. SOLUTION: In a multilayer printed-wiring board consisting of an insulating layer and a wiring layer, a first conductive layer is formed on one surface of a first insulating layer and a second conductive layer forming a wiring pattern on the other surface, and the electronic part is formed on the wiring pattern. In the multilayer printed-wiring board, the first insulating layer has an opening section opened so as to expose part of the first conductive layer, the exposed section of the first conductive layer and a second wiring pattern forming the electronic part are connected electrically by the opening section and the electronic part is embedded by a second insulating layer formed to the other surface. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了解决有源部件的热控制困难的问题，并且由于将安装有源部件和被动部件的基材材料变为半刚性而导致部件的操作的可靠性受损 状态下，由于不包含玻璃布，所以制造时的处理性能劣化，并且具有内置部件的传统布线板即使在产品的可靠性方面也具有不利影响，并且电子部件的周边涂覆有树脂 常规布线板带有内置部件。 解决方案：在由绝缘层和布线层组成的多层印刷电路板中，在第一绝缘层的一个表面和在另一个表面上形成布线图案的第二导电层形成第一导电层， 并且电子部件形成在布线图案上。 在多层印刷电路板中，第一绝缘层的开口部分开放以露出第一导电层的一部分，第一导电层的暴露部分和形成电子部件的第二布线图形电连接 开口部分和电子部件被形成在另一表面上的第二绝缘层嵌入。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008166456A

公开(公告)日：2008-07-17

申请号：JP2006353585

申请日：2006-12-28

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SATO JIN

IPC: H05K1/18 ,  H01L23/12 ,  H05K3/28 ,  H05K3/46

CPC classification number: H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/19105 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a small, thin wiring board which can secure the reliability of a buried component and the reliability of connection with a conductive layer including the component, a component connection and a wiring line and which also can secure an adhesion between the conductive layer and an insulating layer and can attain high-density wiring, and also a method of manufacturing the wiring board. SOLUTION: Wiring patterns 201, 202 and component connections 203a, 203b, 204a, 204b made of conductors such as copper foils are formed on both surfaces of a planar base material 200 made of an electrically insulating material and having a constant thickness. The upper and lower surfaces of the base material 200 other than component mounting openings 209, 210 including the component connections 203a, 203b, 204a, 204b and the upper surface of the wiring patterns 201, 202 are covered with protective layers 207, 208. The protective layers 207, 208 are laminated on the base material 200, and a resistance element 213 and a chip capacitor 214 are buried therein and sealed. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够确保埋入部件的可靠性的小型薄型布线板以及与包括部件，部件连接和布线的导电层的连接的可靠性，并且还可以确保 导电层和绝缘层之间的粘附性并且可以实现高密度布线，以及制造布线板的方法。 解决方案：由电绝缘材料制成并且具有恒定厚度的平面基材200的两个表面上形成有由铜箔等导体构成的布线图案201,202和元件连接件203a，203b，204a，204b。 除了包括部件连接件203a，203b，204a，204b和布线图案201,202的上表面的部件安装开口209,210之外的基材200的上表面和下表面被保护层207,208覆盖。 保护层207,208层叠在基材200上，电阻元件213和片状电容器214埋入其中并密封。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007106007A

公开(公告)日：2007-04-26

申请号：JP2005299683

申请日：2005-10-14

Applicant: Toppan Printing Co Ltd ,  凸版印刷株式会社

Inventor： SATO JIN ,  KAWAMOTO KENJI ,  SEKINE HIDEKATSU

IPC: B32B7/02 ,  H01B5/14 ,  H05K1/16

Abstract: PROBLEM TO BE SOLVED: To provide a laminated product by which the adhesiveness between a dielectric material and capacitor element electrodes can be secured and a capacitor element having a large electric capacitance and excellent reliability can be produced and an electric circuit substrate incorporating the capacitor element using the same.
SOLUTION: The layered product 20 is constituted of a dielectric body layer 13 and an electroconductive body layer 21 adhered to one face of the same. In this case, the dielectric body layer is constituted of a resin and a dielectric powder dispersed in the resin, the content of the dielectric powder in the dielectric layer is low in the electroconductive layer adhesion face side and high in the opposite side of the electroconductive layer adhesion face, thereby the adhesiveness is enhanced.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供可以确保电介质材料和电容器元件电极之间的粘附性的层压产品，并且可以产生具有大电容和优异的可靠性的电容器元件，以及包含 电容元件使用相同。 解决方案：层状产品20由粘合到其一面的电介质体层13和导电体层21构成。 在这种情况下，电介质体层由分散在树脂中的树脂和电介质粉末构成，电介质层中的电介质粉末的含量在导电层粘着面侧低，导电性相反侧高 层粘合面，从而提高粘合性。 版权所有（C）2007，JPO＆INPIT