公开(公告)号：US20250159964A1

公开(公告)日：2025-05-15

申请号：US19021275

申请日：2025-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H10D64/66 ,  H10D64/01 ,  H10D84/85

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US12237394B2

公开(公告)日：2025-02-25

申请号：US18226262

申请日：2023-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US20230369442A1

公开(公告)日：2023-11-16

申请号：US18226264

申请日：2023-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih- Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L27/092

CPC classification number: H01L29/4966 ,  H01L27/092 ,  H01L29/401

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US20230369441A1

公开(公告)日：2023-11-16

申请号：US18226262

申请日：2023-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/40

CPC classification number: H01L29/4966 ,  H01L27/092 ,  H01L29/401

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US11139384B2

公开(公告)日：2021-10-05

申请号：US16561002

申请日：2019-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yun-Tzu Chang ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Shih-Min Chou ,  Yang-Ju Lu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Kuan-Chun Lin ,  Chi-Mao Hsu

IPC: H01L29/43 ,  H01L29/51 ,  H01L29/40 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

公开(公告)号：US20200006514A1

公开(公告)日：2020-01-02

申请号：US16561002

申请日：2019-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yun-Tzu Chang ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Shih-Min Chou ,  Yang-Ju Lu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Kuan-Chun Lin ,  Chi-Mao Hsu

IPC: H01L29/51 ,  H01L29/40 ,  H01L29/49

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

公开(公告)号：US20180331193A1

公开(公告)日：2018-11-15

申请号：US16044581

申请日：2018-07-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Yun-Tzu Chang ,  Wei-Ning Chen ,  Wei-Ming Hsiao ,  Chia-Chang Hsu ,  Kuo-Chih Lai ,  Yang-Ju Lu ,  Yen-Chen Chen ,  Chun-Yao Yang

IPC: H01L29/423 ,  H01L29/51 ,  H01L21/02 ,  H01L29/49 ,  H01L29/06 ,  H01L27/092 ,  H01L27/088 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/42356 ,  H01L21/02183 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/518

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

公开(公告)号：US09691704B1

公开(公告)日：2017-06-27

申请号：US15175299

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chia-Chang Hsu ,  Nien-Ting Ho ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Shih-Min Chou ,  Yun-Tzu Chang ,  Yang-Ju Lu ,  Wei-Ming Hsiao ,  Wei-Ning Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/76 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.

公开(公告)号：US11538917B2

公开(公告)日：2022-12-27

申请号：US17353830

申请日：2021-06-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Hsin Hsu ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Shih-Min Chou ,  Nien-Ting Ho ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer and a titanium aluminide layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and a thickness of the titanium aluminide layer ranges from twice a thickness of the titanium nitride barrier layer to three times the thickness of the titanium nitride barrier layer.

公开(公告)号：US11424408B2

公开(公告)日：2022-08-23

申请号：US17384817

申请日：2021-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Kuo-Chih Lai ,  Wei-Ming Hsiao ,  Hui-Ting Lin ,  Szu-Yao Yu ,  Nien-Ting Ho ,  Hsin-Fu Huang ,  Chin-Fu Lin

IPC: H01L21/02 ,  H01L45/00

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.