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    SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
    22.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开

    公开(公告)号：US20180138263A1

    公开(公告)日：2018-05-17

    申请号：US15350453

    申请日：2016-11-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ko-Wei Lin ,  Yen-Chen Chen ,  Chin-Fu Lin ,  Chun-Yuan Wu ,  Chun-Ling Lin

    IPC: H01L49/02

    CPC classification number: H01L28/75

    Abstract: A semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode. The bottom electrode includes a first layer and a second layer disposed on the first layer. The bottom electrode is formed of TiN. The first layer has a crystallization structure. The second layer has an amorphous structure. The first high-k dielectric layer is disposed on the bottom electrode. The first high-k dielectric layer is formed of TiO2. The second high-k dielectric layer is disposed on the first high-k dielectric layer. The second high-k dielectric layer is formed of a material different from TiO2. The top electrode is disposed on the second high-k dielectric layer.

    METHOD OF FORMING INTER-LEVEL DIELECTRIC LAYER
    24.
    发明申请
    METHOD OF FORMING INTER-LEVEL DIELECTRIC LAYER 审中-公开
    形成层间电介质层的方法

    公开(公告)号：US20150206803A1

    公开(公告)日：2015-07-23

    申请号：US14158857

    申请日：2014-01-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Hsin Liu ,  Tzu-Chin Wu ,  Jei-Ming Chen ,  Yu-Ren Wang ,  Chun-Yuan Wu ,  Chin-Fu Lin

    IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105

    CPC classification number: H01L21/823462 ,  H01L21/31116 ,  H01L21/76837 ,  H01L21/823475

    Abstract: A method of forming an inter-level dielectric layer including the following step is provided. Two gate structures are formed on a substrate. A first oxide layer is formed to conformally cover the two gate structures and the substrate. The first oxide layer is etched ex-situ by a high density plasma (HDP) etching process. A second oxide layer is formed in-situ on the first oxide layer and fills a gap between the two gate structures by a high density plasma (HDP) depositing process.

    Abstract translation: 提供一种形成包括以下步骤的层间电介质层的方法。 在基板上形成两个栅极结构。 形成第一氧化物层以保形地覆盖两个栅极结构和衬底。 通过高密度等离子体（HDP）蚀刻工艺非原位蚀刻第一氧化物层。 在第一氧化物层上原地形成第二氧化物层，并通过高密度等离子体（HDP）沉积工艺填充两个栅极结构之间的间隙。

    MULTIGATE FIELD EFFECT TRANSISTOR AND PROCESS THEREOF
    25.
    发明申请
    MULTIGATE FIELD EFFECT TRANSISTOR AND PROCESS THEREOF 有权
    多功能场效应晶体管及其过程

    公开(公告)号：US20140117455A1

    公开(公告)日：2014-05-01

    申请号：US13662561

    申请日：2012-10-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Chien Liu ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chin-Cheng Chien ,  Chia-Lin Hsu

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/785 ,  H01L21/02225 ,  H01L21/764 ,  H01L27/11 ,  H01L29/66484 ,  H01L29/66795

    Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.

    Abstract translation: 多栅场效应晶体管包括两个鳍状结构和介电层。 鳍状结构位于基底上。 电介质层覆盖基板和鳍状结构。 在两个鳍状结构之间的电介质层中至少有两个空隙。 此外，本发明还提供了一种用于形成所述多栅极场效应晶体管的多栅场效应晶体管工艺，包括以下步骤。 在基板上形成两个鳍状结构。 介电层覆盖基板和两个鳍状结构，其中在两个鳍状结构之间的电介质层中形成至少两个空隙。

    METHOD OF FORMING OPENING ON SEMICONDUCTOR SUBSTRATE
    26.
    发明申请
    METHOD OF FORMING OPENING ON SEMICONDUCTOR SUBSTRATE 有权
    在半导体基板上形成开路的方法

    公开(公告)号：US20140106568A1

    公开(公告)日：2014-04-17

    申请号：US14142940

    申请日：2013-12-30

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Po-Chun Chen

    IPC: H01L21/311

    CPC classification number: H01L21/31144 ,  H01L21/76802

    Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.

    Abstract translation: 本发明提供一种在半导体衬底上形成开口的方法。 首先，提供基板。 然后在基板上形成介电层和盖层。 电介质层的厚度和盖层的厚度之比基本上在15和1.5之间。 接下来，在盖层上形成图案化的氮化硼层。 最后，通过使用图案化的硬掩模作为掩模来执行蚀刻工艺，以蚀刻覆盖层和电介质层，以在盖层和电介质层中形成开口。

    NON-PLANAR SEMICONDUCTOR STRUCTURE
    27.
    发明申请
    NON-PLANAR SEMICONDUCTOR STRUCTURE 有权
    非平面半导体结构

    公开(公告)号：US20130228836A1

    公开(公告)日：2013-09-05

    申请号：US13869037

    申请日：2013-04-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

    IPC: H01L29/78

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. Anon-planar semiconductor process is also provided for forming the semiconductor structure.

    Abstract translation: 非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。 鳍状结构位于基底上。 隔离结构位于鳍状结构之间，隔离结构具有含氮层。 外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。 还提供了用于形成半导体结构的非平面半导体工艺。

    SEMICONDUCTOR STRUCTURE WITH AN EPITAXIAL LAYER
    29.
    发明申请
    SEMICONDUCTOR STRUCTURE WITH AN EPITAXIAL LAYER 有权

    公开(公告)号：US20210242018A1

    公开(公告)日：2021-08-05

    申请号：US17218112

    申请日：2021-03-30

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsiao-Pang Chou ,  Hon-Huei Liu ,  Ming-Chang Lu ,  Chin-Fu Lin ,  Yu-Cheng Tung

    IPC: H01L21/02 ,  H01L29/20 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L23/00

    Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.

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