公开(公告)号：US09761657B2

公开(公告)日：2017-09-12

申请号：US14952877

申请日：2015-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L29/78 ,  G06F17/50 ,  H01L23/535

CPC classification number: H01L29/4238 ,  G06F17/5072 ,  H01L23/535 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/785

Abstract: A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v.

公开(公告)号：US20250048671A1

公开(公告)日：2025-02-06

申请号：US18459454

申请日：2023-09-01

Applicant: United Microelectronics Corp.

Inventor： Hsuan-Kai Chen ,  Tun-Jen Cheng ,  Ching-Chung Yang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423

Abstract: A transistor structure including a substrate, a gate dielectric layer, a gate, a first doped region, a second doped region, a first drift region, and a dummy gate is provided. The gate dielectric layer is located on the substrate. The gate dielectric layer includes first and second portions. The second portion is connected to the first portion. The thickness of the second portion is greater than the thickness of the first portion. The gate is located on the first and second portions. The first doped region and the second doped region are located in the substrate on two sides of the gate dielectric layer. The first drift region is located in the substrate on one side of the gate. The second doped region is located in the first drift region. The dummy gate is located on the second portion between the gate and the second doped region.

公开(公告)号：US12206020B2

公开(公告)日：2025-01-21

申请号：US18139964

申请日：2023-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Nien-Chung Li ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

公开(公告)号：US20220209009A1

公开(公告)日：2022-06-30

申请号：US17159166

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Nien-Chung Li ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

公开(公告)号：US10453938B2

公开(公告)日：2019-10-22

申请号：US15846150

申请日：2017-12-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Chang-Po Hsiung ,  Chia-Wen Lu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

公开(公告)号：US20190103460A1

公开(公告)日：2019-04-04

申请号：US15720204

申请日：2017-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Chia-Lin Wang ,  Chia-Wen Lu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A semiconductor transistor device is provided. The semiconductor transistor device includes a semiconductor substrate, a gate structure, a first isolation structure, a first doped region, and a first extra-contact structure. The gate structure is disposed on the semiconductor substrate, and the semiconductor substrate has a first region and a second region respectively located on two opposite sides of the gate structure. The first isolation structure and the first doped region are disposed in the first region of the semiconductor substrate. The first extra-contact structure is disposed on the semiconductor structure. The first extra-contact structure is located between the gate structure and the first doped region and penetrating into the first isolation structure in the first region of the semiconductor substrate, and the first doped region is electrically coupled to the first extra-contact structure.

公开(公告)号：US09972678B2

公开(公告)日：2018-05-15

申请号：US15287535

申请日：2016-10-06

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/51 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.

公开(公告)号：US09852952B2

公开(公告)日：2017-12-26

申请号：US14925955

申请日：2015-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chung Wang ,  Shih-Yin Hsiao ,  Wen-Fang Lee ,  Nien-Chung Li ,  Shu-Wen Lin

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/49 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/28035 ,  H01L21/31051 ,  H01L21/32115 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/4916 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7834

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.

公开(公告)号：US20170330948A1

公开(公告)日：2017-11-16

申请号：US15668708

申请日：2017-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Chih-Chung Wang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  G06F17/50

CPC classification number: H01L29/4238 ,  G06F17/5072 ,  H01L23/535 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/785

Abstract: A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.

公开(公告)号：US09741850B1

公开(公告)日：2017-08-22

申请号：US15235320

申请日：2016-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Kuan-Liang Liu ,  Kai-Kuen Chang

IPC: H01L29/745 ,  H01L29/76 ,  H01L23/58 ,  H01L21/00 ,  H01L21/336 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/1087 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7834

Abstract: A semiconductor device having a substrate, a gate electrode, a source and a drain, and a buried gate dielectric layer is disclosed. The buried gate dielectric layer is disposed below said gate electrode and protrudes therefrom to said drain, thereby separating said gate electrode and said drain by a substantial distance to reduce gate induced drain leakage.