公开(公告)号：WO2017039829A1

公开(公告)日：2017-03-09

申请号：PCT/US2016/041128

申请日：2016-07-06

Applicant: XILINX, INC.

Inventor： AMIR-ASLANZADEH, Hesam ,  UPADHYAYA, Parag

IPC: H04L27/36

CPC classification number: H04B17/12 ,  H04L27/2631 ,  H04L27/362 ,  H04L2027/0057

Abstract: An apparatus (100), and method (600) therefor, relate generally to broadband IQ generation. In this apparatus (100), related generally to broadband in-phase and quadrature phase ("IQ") generation, a divider circuit (132) and a polyphase filter circuit (130) are configured for receiving an oscillator output (123). The polyphase filter circuit (130) is configured for polyphase filtering the oscillator output (123) into a first quadrature output (136). The divider circuit (132) is configured for dividing the oscillator output (123) into a second quadrature output (135). A multiplexer circuit (137) is coupled to the divider circuit (132) and the polyphase filter circuit (130) and configured for selecting either the first quadrature output (1 36) or the second quadrature output (135) as an IQ output (139) based on a bandwidth of the oscillator output (123).

Abstract translation: 一种装置（100）及其方法（600）通常涉及宽带IQ生成。 在该设备（100）中，分配电路（132）和多相滤波器电路（130）通常与宽带同相和正交相位（“IQ”）生成相关，用于接收振荡器输出（123）。 多相滤波器电路（130）被配置为将振荡器输出（123）多相滤波成第一正交输出（136）。 分频器电路（132）被配置为将振荡器输出（123）分成第二正交输出（135）。 多路复用器电路（137）耦合到分频器电路（132）和多相滤波器电路（130），并被配置为选择第一正交输出（16）或第二正交输出（135）作为IQ输出（139 ）基于振荡器输出（123）的带宽。

公开(公告)号：WO2016176205A1

公开(公告)日：2016-11-03

申请号：PCT/US2016/029361

申请日：2016-04-26

Applicant: XILINX, INC.

Inventor： UPADHYAYA, Parag ,  BEKELE, Adebabay, M. ,  TURKER MELEK, Didem, Z. ,  WU, Zhaoyin, D.

IPC: H03L7/18 ,  H03L7/197

CPC classification number: H03L7/095 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1974 ,  H03M3/30 ,  H04B1/50

Abstract: In an example, a phase-locked loop (PLL) circuit (108) includes an error detector (202) operable to generate an error signal; an oscillator (204) operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider (208) operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) (209) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine (214) operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.

Abstract translation: 在一个示例中，锁相环（PLL）电路（108）包括可操作以产生误差信号的误差检测器（202） 振荡器（204），其可操作以提供具有基于所述误差信号和频带选择信号的输出频率的输出信号，所述输出频率是倍频器乘以参考频率; 分频器（208），其可操作以分割所述输出信号的输出频率以基于分频器控制信号产生反馈信号; Σ-Δ调制器（SDM）（209），其可操作以基于表示所述倍频器的整数值和分数值的输入产生所述除法器控制信号，所述SDM响应于可操作以选择所述乘法器的顺序的顺序选择信号 SDM; 以及状态机（214），其可操作以在获取状态下生成所述频带选择信号并设置所述SDM的顺序。

公开(公告)号：WO2016099722A1

公开(公告)日：2016-06-23

申请号：PCT/US2015/060379

申请日：2015-11-12

Applicant: XILINX, INC.

Inventor： BEKELE, Adebabay, M. ,  UPADHYAYA, Parag

IPC: H03B5/12

CPC classification number: H03B5/1253 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1271 ,  H03B5/1278 ,  H03B5/129 ,  H03B2201/0208 ,  H03B2201/0266 ,  H03B2201/0291 ,  H03B2201/031 ,  H03B2201/038

Abstract: Voltage-controlled oscillation (100) is described. In an apparatus therefor, an inductor (120) has a tap and has or is coupled to a positive-side output node (105) and a negative side output node (106). The tap is coupled to receive a first current. A coarse grain capacitor array (130) is coupled to the positive-side output node (105) and the negative side output node (106) and is coupled to respectively receive select signals (168). A varactor (140) is coupled to the positive-side output node (105) and the negative side output node (106) and is coupled to receive a control voltage (143). The varactor (140) includes MuGFETs (141, 142). A transconductance cell (150) is coupled to the positive- side output node (105) and the negative side output node (106), and the transconductance cell (150) has a common node (107). A frequency scaled resistor network (160) is coupled to the common node (107) and is coupled to receive the select signals (168) for a resistance for a path for a second current.

Abstract translation: 描述了压控振荡（100）。 在其装置中，电感器（120）具有抽头并且具有或耦合到正侧输出节点（105）和负侧输出节点（106）。 抽头被耦合以接收第一电流。 粗粒电容器阵列（130）耦合到正侧输出节点（105）和负侧输出节点（106），并被耦合以分别接收选择信号（168）。 变容二极管（140）耦合到正侧输出节点（105）和负侧输出节点（106），并耦合以接收控制电压（143）。 变容二极管（140）包括MuGFET（141,142）。 跨导单元（150）耦合到正侧输出节点（105）和负侧输出节点（106），并且跨导单元（150）具有公共节点（107）。 频率比例电阻器网络（160）耦合到公共节点（107），并被耦合以接收用于第二电流的路径的电阻的选择信号（168）。

公开(公告)号：WO2013036306A1

公开(公告)日：2013-03-14

申请号：PCT/US2012/039898

申请日：2012-05-29

Applicant: XILINX, INC. ,  WU, Zhaoyin, D. ,  UPADHYAYA, Parag ,  JIANG, Xuewen

Inventor： WU, Zhaoyin, D. ,  UPADHYAYA, Parag ,  JIANG, Xuewen

IPC: H01L49/02

CPC classification number: H01L28/86 ,  Y10T29/43

Abstract: An interdigitated capacitor having digits of varying width is disclosed. One embodiment of a capacitor (100) includes a first plurality of conductive digits (110) and a second plurality of conductive digits (110) positioned in an interlocking manner with the first plurality of conductive digits (110), such that an interdigitated structure is formed. The first plurality of conductive digits (110) and the second plurality of conductive digits (110) collectively form a set of digits, where the width of a first digit in the set of digits (110) is non-uniform with respect to a second digit in the set of digits.

Abstract translation: 公开了具有变化宽度的数字的交错电容器。 电容器（100）的一个实施例包括与第一多个导电数字（110）以互锁方式定位的第一多个导电数字（110）和第二多个导电数字（110），使得叉指式结构 形成。 第一多个导电数字（110）和第二多个导电数字（110）共同形成一组数字，其中数字组（110）中的第一数字的宽度相对于第二数字（110）是不均匀的 数字组中的数字。

公开(公告)号：WO2012050703A1

公开(公告)日：2012-04-19

申请号：PCT/US2011/051247

申请日：2011-09-12

Applicant: XILINX, INC.

Inventor： KIREEV, Vassili ,  UPADHYAYA, Parag ,  MARLETT, Mark, J.

IPC: H01F17/00

CPC classification number: H01F17/0013 ,  H01F2017/0073 ,  Y10T29/4902

Abstract: A symmetrical inductor includes pairs of half-loops (e.g., 312, 314, 316, 318), first and second terminal electrodes (e.g., 302, 304), and a center-tap electrode (e.g., 310). The half-loop pairs are in respective conductive layers (e.g., 101, 201 ) of an integrated circuit. Each half-loop pair includes a first (e.g., 312, 316) and second half-loop (e.g., 314, 318) in the respective conductive layer. The first and second terminal electrodes are in a first conductive layer, and the center-tap electrode is in a second conductive layer. The first terminal electrode and the center-tap electrode are coupled through a first series combination that includes the first half-loop of each half-loop pair. The second terminal electrode and the center-tap electrode are coupled through a second series combination that includes the second half-loop of each half-loop pair.

Abstract translation: 对称电感器包括一对半环（例如，312,314,316,318），第一和第二端子电极（例如，302,304）和中心抽头电极（例如310）。 半环对在集成电路的各个导电层​​（例如，101,201）中。 每个半环对包括相应导电层中的第一（例如312,316）和第二半环（例如，314,318）。 第一和第二端子电极在第一导电层中，中心抽头电极处于第二导电层中。 第一端子电极和中心抽头电极通过包括每个半环对的第一半环的第一串联组合耦合。 第二端子电极和中心抽头电极通过包括每个半环对的第二半环的第二串联组合耦合。

公开(公告)号：WO2022271254A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/023364

申请日：2022-04-04

Applicant: XILINX, INC.

Inventor： WU, Zhaoyin Daniel ,  UPADHYAYA, Parag ,  SHI, Hong

IPC: H01L23/64 ,  H01F17/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/528 ,  H01L21/60 ,  H01L23/522 ,  H01F17/0006 ,  H01F2017/0073 ,  H01L2223/6638 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/16 ,  H01L25/0655 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01Q1/2283

Abstract: A package device comprises a first transceiver (110) comprising a first integrated circuit (IC) die and transmitter circuitry (112), and a second transceiver (120) comprising a second IC die and receiver circuitry (124). The receiver circuitry is coupled to the transmitter circuitry via a channel (140). The package device further comprises an interconnection device (130) connected to the first IC die and the second IC die. The interconnection device comprises the channel (140) connecting the transmitter circuitry with the receiver circuitry, and a passive inductive element (142) disposed external to the first IC die and the second IC die and along the channel.

公开(公告)号：WO2021015867A1

公开(公告)日：2021-01-28

申请号：PCT/US2020/036216

申请日：2020-06-04

Applicant: XILINX, INC.

Inventor： POON, Chi, Fung ,  LARABA, Asma ,  UPADHYAYA, Parag

IPC: G06F1/10

Abstract: A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit (1102) configured to receive input data at a first input (1106) and generate output data at a first output (1108), wherein the output data is based upon the input data and a function of the main circuit; a replica circuit (1104) configured to receive calibration data at a second input (1114) and generate calibration output data, based upon the calibration data, at a second output (1118), wherein the replica circuit provides a replica function of the function of the main circuit; and a calibration circuit (1120) configured to receive the output data from the main circuit during a foreground calibration mode, and the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides control signals to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.

公开(公告)号：WO2020041601A1

公开(公告)日：2020-02-27

申请号：PCT/US2019/047725

申请日：2019-08-22

Applicant: XILINX, INC.

Inventor： MA, Shaojun ,  UPADHYAYA, Parag ,  TURKER MELEK, Didem Z.

IPC: H03K19/0175 ,  H03K19/0185 ,  H04B3/04 ,  H03K19/00

Abstract: Methods and apparatus relate to a bidirectional differential interface (300) having a voltage-mode transmit driver architecture (325) formed of multiple selectively enabled slices for coarse output resistance impedance matching. In examples, the transmit driver (325) may include a programmable resistance (340) for fine-tuning to impedance match the output resistance for transmit operation. During receive operation, protective voltage may be proactively applied to gates of drive transistors to minimize voltage stresses applied by external signal sources. Some implementations may automatically float the sources of the drive transistors to prevent back-feeding externally driven signal currents during receive mode operations. The transmit driver (325) may have programmable voltage swing on, for example, the upper and/or lower bounds to enhance compatibility. A programmable common mode voltage node may be selectively applied in a termination network (335), for example, through common mode resistors for receive mode operations.

公开(公告)号：WO2019143431A1

公开(公告)日：2019-07-25

申请号：PCT/US2018/065826

申请日：2018-12-14

Applicant: XILINX, INC.

Inventor： WU, Zhaoyin, D. ,  UPADHYAYA, Parag ,  CHANG, Kun-Yung

IPC: H01L23/522

Abstract: Examples herein describe techniques for isolating portions of an IC (100) that include sensitive components (e.g., inductors or capacitors) from return current (330) in a grounding plane (415). An output current generated by a transmitter (105) or driver in an IC can generate a magnetic field (405) which induces return current in the grounding plane. If the return current is proximate the sensitive components (305), the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots (500) through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.

公开(公告)号：WO2018053137A1

公开(公告)日：2018-03-22

申请号：PCT/US2017/051574

申请日：2017-09-14

Applicant: XILINX, INC.

Inventor： JING, Jing ,  WU, Shuxian ,  WU, Xin, X. ,  UPADHYAYA, Parag

IPC: H01L23/522

CPC classification number: H01L23/5227 ,  H01L23/5225 ,  H01L23/645 ,  H01L28/10

Abstract: A semiconductor device (300) includes an interconnect structure (306) disposed over a semiconductor substrate ( 302). The interconnect structure includes a first device (330) disposed in a first portion (306-1 ) of the interconnect structure. A first shielding plane (402) including a first conductive material is disposed in a second portion (306-2) of the interconnect structure over the first portion of the interconnect structure. A second device (504) is disposed in a third portion (306-3) of the interconnect structure over the second portion of the interconnect structure. An isolation wall (320) including a second conductive material is disposed in the first, second, and third portions of the interconnect structure. The isolation wall is coupled to the first shielding plane, and surrounds the first device, the first shielding plane, and the second device.

Abstract translation: 半导体器件（300）包括设置在半导体衬底（302）上的互连结构（306）。 互连结构包括布置在互连结构的第一部分（306-1）中的第一器件（330）。 包括第一导电材料的第一屏蔽平面（402）设置在互连结构的第一部分上的互连结构的第二部分（306-2）中。 第二器件（504）设置在互连结构的第二部分上方的互连结构的第三部分（306-3）中。 包括第二导电材料的隔离壁（320）设置在互连结构的第一部分，第二部分和第三部分中。 隔离壁耦合到第一屏蔽平面，并围绕第一装置，第一屏蔽平面和第二装置。