公开(公告)号：JP2006262104A

公开(公告)日：2006-09-28

申请号：JP2005077009

申请日：2005-03-17

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MAEJIMA TOSHIO

IPC: H03F3/217

Abstract: PROBLEM TO BE SOLVED: To input an input signal whose level changes in positive and negative polarities around an OV without being restricted up to a supply voltage and to make an output almost OV at inputting nothing.
SOLUTION: A D level amplifier operated by a single power supply has a differential integrator and a PWM modulator. The differential integrator integrates a difference between a plus side input signal and a minus side input signal which make analog input signals. The PWM modulator outputs a pulse train signal with a pulse width according to the signal level in the positive term of the analog input signals from a first output terminal and outputs the pulse train signal with the pulse width according to the signal level in the negative term of the analog input signals from a second output terminal, based on the output of the differential integrator. The D level amplifier has a protection circuit to restrict an excessive input voltage. The differential integrator includes an operational amplifier where a voltage level of the analog input signals having the positive and negative polarities around the OV can operate near the OV.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了输入在0V周围的正极性和负极性电平变化的输入信号，而不受限于电源电压，并且在不输入任何情况下将输出几乎为0V。 解决方案：由单个电源运行的D电平放大器具有差分积分器和PWM调制器。 差分积分器集成了正侧输入信号和进行模拟输入信号的负侧输入信号之间的差异。 PWM调制器根据来自第一输出端的模拟输入信号的正项中的信号电平输出具有脉冲宽度的脉冲串信号，并根据负项中的信号电平输出具有脉冲宽度的脉冲序列信号 的来自第二输出端的模拟输入信号，基于差分积分器的输出。 D电平放大器具有保护电路以限制过大的输入电压。 差分积分器包括运算放大器，其中具有OV周围的正极性和负极性的模拟输入信号的电压电平可以在OV附近运行。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005217710A

公开(公告)日：2005-08-11

申请号：JP2004020978

申请日：2004-01-29

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MAEJIMA TOSHIO

IPC: H03G3/10 ,  H03G3/02

Abstract: PROBLEM TO BE SOLVED: To provide an electronic volume having almost no error from a theoretical value and usable for a circuit of a single power supply.
SOLUTION: An output of an operational amplifier OPA 1 is a signal inverse of Vin resulting from inverting an input signal Vin on the basis of a reference voltage Vt. When switches Sk, Sk' are closed (the other switches are open), a signal resulting from applying resistance division to the signal Vin is applied to a noninverting input terminal of an operational amplifier OPA 2, and a signal resulting from applying resistance division to the signal inverse of Vin is applied to a noninverting input terminal of an operational amplifier OPA 3. The signals are amplified at the unity gain by the operational amplifiers OPA2, 3 and an operational amplifier OPA4 applies differential amplification to the amplified signal. Since the signals via the switches Sk, Sk' are inverse to each other with respect to the reference voltage Vt, when the operational amplifier OPA 4 applies differential amplification to the signal, a signal resulting from amplifying the signal via the switch Sk is outputted from its output terminal.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供几乎没有理论值的误差并且可用于单个电源的电路的电子体积。 解决方案：运算放大器OPA 1的输出是基于参考电压Vt使输入信号Vin反相而产生的Vin的信号倒数，当开关Sk，Sk'闭合（其他开关断开）时， 通过对信号Vin施加电阻分割而产生的信号被施加到运算放大器OPA 2的非反相输入端，并且将对Vin的信号反相施加电阻分频产生的信号施加到操作的非反相输入端 放大器OPA 3.信号以运算放大器OPA2,3的单位增益放大，运算放大器OPA4对放大的信号进行差分放大。 由于通过开关Sk，Sk'的信号相对于参考电压Vt彼此相反，当运算放大器OPA4对信号施加差分放大时，从经由开关Sk放大信号而产生的信号从 其输出端子。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004282714A

公开(公告)日：2004-10-07

申请号：JP2004013361

申请日：2004-01-21

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MAEJIMA TOSHIO

IPC: H03F3/217

CPC classification number: H03F3/2173 ,  H03F3/2171 ,  H03F2200/351

Abstract: PROBLEM TO BE SOLVED: To provide a pulse width modulation amplifier capable of reducing an EMI which can be contained in a pulse width modulation output while reducing a manufacturing cost.
SOLUTION: An input signal is converted to an analog signal PLLC with the aid of FETs 102, 103 and constant current sources 104, 105 from a phase comparator 101, which is in turn supplied to a capacitor 107, and whose electric potential serves as an electric potential of a gate of an FET 110, and a current according to the electric potential is conducted through an FET 112. The current through the FET 112 and a current conducted through FETs 116, 117 are same each other and serve to determine the inclination of a triangular wave generated, so that the electric potential of the FET 110 determines the inclination of the triangular wave generated. The capacitor 34 is controlled on whether or not it is connected to the capacitor 107 for every period of a signal NFB through a D flip-flop 31, switching elements 32, 33, and the capacitor 34. Even when the same signal PLLC is supplied, the electric potential of the FET 110 is varied, and hence the period of the triangular wave generated is varied. Therefore, provided the input signal is output after subjected to pulse width modulation amplification, the EMI is reduced.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2002344258A

公开(公告)日：2002-11-29

申请号：JP2001145328

申请日：2001-05-15

Applicant: YAMAHA CORP

Inventor： MAEJIMA TOSHIO ,  TODA AKIHIKO

IPC: G05F1/59 ,  H03F1/02 ,  H03F1/30 ,  H03F3/34 ,  H03F3/45 ,  H03K5/02

Abstract: PROBLEM TO BE SOLVED: To provide a level shift circuit that does not require exterior capacitors, and at the same time, requires only one reference voltage. SOLUTION: This level shift circuit 11 comprises an operational amplifier 12, an input resistor 13 whose one end is connected to the output terminal of an amplification circuit 4 and the other is connected to the inverted input end of the operational amplifier 12, a resistor 14 (a value R0) for level shift, whose one end is connected to the inverted input end of the operational amplifier 12 and the other is grounded, and a feedback resistor 15 (value R1) of the operational amplifier 12. In this case, a reference voltage Vref is applied to the non-inverted input terminal of the operational amplifier 12. The output signal of the level shift circuit 11 turns into a signal, where the output of the amplification circuit 4 is shifted by a fixed amount (code W3). The amount ▵V of shift becomes ▵V=Vc-Vref=(R1/R0)Vref, when the amplitude center of the output signal in the level shift circuit 11 is set to Vc.

公开(公告)号：JP2000082923A

公开(公告)日：2000-03-21

申请号：JP17861899

申请日：1999-06-24

Applicant: YAMAHA CORP

Inventor： MAEJIMA TOSHIO

IPC: G01R19/22 ,  H03D1/18

Abstract: PROBLEM TO BE SOLVED: To provide a full-wave rectifier circuit which can be easily integrated even in a MOS process and does not use a diode as an external parts. SOLUTION: The signals of an inverter amplifier 10 and a non-inverter amplifier 20 are supplied to the gates of N-channel FET N5 and N6 related to an output part 30 respectively. The FET N5 and N6 absorb the currents which are accordant with gate voltage VG1 and VG2 respectively. As the output signals of both amplifiers 10 and 20 have phases different from each other by 180 deg., one of both FET N5 and N6 always absorbs a current to drop the voltage of an output signal Vout compared with the reference voltage Vr. Meanwhile, the other FET functions to raise the signal Vout and accordingly its gate voltage drops. In this case, however, the voltage of the signal Vout never rises since one of both FETs absorbs a current. As a result, the gate voltage of one of both FETs is set at a ground level with the other FET turned off. Thus, a fully rectified output signal Vout is produced.

公开(公告)号：JPH10143262A

公开(公告)日：1998-05-29

申请号：JP30512896

申请日：1996-11-15

Applicant: YAMAHA CORP

Inventor： MAEJIMA TOSHIO

IPC: G05F3/24 ,  G05F3/26

Abstract: PROBLEM TO BE SOLVED: To provide a constant current circuit which can output a constant current not depending on a power supply voltage, and of which chip area can be reduced. SOLUTION: This constant current circuit is composed of 1st and 2nd current sources A1 and A2 for respectively outputting mutually different currents i4 and i7 depending on a common power supply voltage V, current attenuation circuit D for attenuating the current i4 outputted from the current source A1 and outputting a current i9, current adder circuit P for adding the current i9 outputted from the current attenuation circuit D and the current i7 outputted from the current source A2, and current output circuit O for outputting a current i10 provided by the current adder circuit P through current output terminals Iout1, Iout2.... When the Tr sizes of respective parts are set so that the inclination of current i9 flowing through a PMOS transistor Tr 9 can be equal with the inclination of current i7 flowing through an NMOS transistor Tr 7, the constant current not depending on the power supply voltage V can be obtained within the range higher than V1.

公开(公告)号：JPH08125462A

公开(公告)日：1996-05-17

申请号：JP28414094

申请日：1994-10-25

Applicant: YAMAHA CORP

Inventor： MAEJIMA TOSHIO

IPC: H03H19/00 ,  H03F3/45 ,  H03G11/02 ,  H03M3/02

Abstract: PURPOSE: To obtain the CMOS differential amplifier circuit in which fluctuation in an operating point is effectively suppressed. CONSTITUTION: Amplitude limit circuits 21, 22 are provided in a feedback circuit of a CMOS operational amplifier 20. The amplitude limit circuit 21 is made up of two PMOS TRs QP11, QP14 of diode connection which are connected between input and output in opposite polarity to each other and two NMOS TRs QN12, QN13 of diode connection which are connected between input and output in opposite polarity to each other similarly. The other amplitude limit circuit 22 is made up of two PMOS TRs QP21, QP24 of diode connection and two NMOS TRs QN22, QN23 of diode connection similarly.

公开(公告)号：JP2012175420A

公开(公告)日：2012-09-10

申请号：JP2011035739

申请日：2011-02-22

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KAWAGISHI NORIHIRO ,  TSUJI NOBUAKI ,  MAEJIMA TOSHIO

IPC: H03F3/347 ,  G05F1/10

Abstract: PROBLEM TO BE SOLVED: To provide a constant current circuit that has a small variation in current value.SOLUTION: P-channel transistors 3, 9 function as first and second constant current sources for outputting proportional constant currents. A capacitor 5 is connected in series with the P-channel transistor 3. An N-channel transistor 6 as a discharge switch periodically discharges the capacitor 5 of a stored charge. A comparator 7 turns on P-channel transistors 4, 10 to output the currents from the first and second constant current sources as long as a charge voltage V1 of the capacitor 5 is within a reference voltage Va. A smoothing circuit 19 comprising a capacitor 11, a resistance 12 and a capacitor 13 smooths the output current of the second constant current source. An output current mirror comprising N-channel transistors 14, 15 outputs a current proportional to the current smoothed by the smoothing circuit 19.

Abstract translation: 要解决的问题：提供电流值变化小的恒流电路。 解决方案：P沟道晶体管3,9用作用于输出比例恒定电流的第一和第二恒定电流源。 电容器5与P沟道晶体管3串联连接。作为放电开关的N沟道晶体管6对存储电荷的电容器5进行周期性的放电。 只要电容器5的充电电压V1在参考电压Va内，比较器7接通P沟道晶体管4,10来输出来自第一和第二恒定电流源的电流，平滑电路19包括电容器11 电阻12和电容器13平滑第二恒定电流源的输出电流。 包括N沟道晶体管14,15的输出电流镜输出与平滑电路19平滑化的电流成比例的电流。（C）2012，JPO＆INPIT

公开(公告)号：JP2012070501A

公开(公告)日：2012-04-05

申请号：JP2010211703

申请日：2010-09-22

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KAWAGISHI NORIHIRO ,  TSUJI NOBUAKI ,  MAEJIMA TOSHIO

IPC: H02M3/155

CPC classification number: H02M3/156 ,  H02M2001/0032 ,  Y02B70/16

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption under low load without requiring signals and circuits of two systems.SOLUTION: A voltage generation circuit 100 brings a transistor TR1, which is connected to a DC power source 12, into conduction by supplying a driving pulse PDR1 and generates an output voltage VOUT. A voltage detection circuit 30 generates a detection voltage VD according to the output voltage VOUT. A reference generation circuit 40 generates a reference voltage VREF which changes periodically. A comparison circuit 50 generates a control signal X, in which a control pulse PX having a pulse width WX corresponding to the detection voltage VD is sequentially set, according to a comparison result of the detection voltage VD and the reference voltage VREF. A driving pulse generation circuit 60 generates a driving pulse PDR1 corresponding to the control pulse PX and supplies it to the transistor TR1 when the pulse width WX of the control pulse PX is wider than a prescribed width. The driving pulse generation circuit 60 stops the generation of the driving pulse PDR1 when the pulse width WX of the control pulse PX is narrower than the prescribed width.

Abstract translation: 要解决的问题：为了在低负载下降低功耗，不需要两个系统的信号和电路。 解决方案：电压产生电路100通过提供驱动脉冲PDR1将连接到DC电源12的晶体管TR1导通，并产生输出电压VOUT。 电压检测电路30根据输出电压VOUT产生检测电压VD。 参考产生电路40产生周期性变化的参考电压VREF。 比较电路50根据检测电压VD和参考电压VREF的比较结果产生控制信号X，其中依次设置具有与检测电压VD相对应的脉冲宽度WX的控制脉冲PX。 驱动脉冲产生电路60产生与控制脉冲PX对应的驱动脉冲PDR1，并且当控制脉冲PX的脉冲宽度WX比规定宽度宽时，将其提供给晶体管TR1。 当控制脉冲PX的脉冲宽度WX比规定宽度窄时，驱动脉冲产生电路60停止产生驱动脉冲PDR1。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2011130067A

公开(公告)日：2011-06-30

申请号：JP2009285063

申请日：2009-12-16

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TSUJI NOBUAKI ,  MAEJIMA TOSHIO

IPC: H03F3/34 ,  H03F3/45 ,  H03F3/68 ,  H03M1/68 ,  H03M1/74

CPC classification number: H03F3/45183 ,  H03F3/45475 ,  H03F2203/45138 ,  H03F2203/45674

Abstract: PROBLEM TO BE SOLVED: To reduce errors of operation results of a voltage adder circuit configured by connecting output terminals of two operational amplifiers through two resistors. SOLUTION: The voltage adder circuit 50 includes two operational amplifiers OP1, OP2 and resistors ra, rb inserted between the output terminals OUT of the operational amplifiers OP1, OP2. Voltages Va, Vb are applied to respective positive phase input terminals IN+ of the operational amplifiers OP1, OP2, and a voltage Vo to which the voltages Va, Vb are weighted added is output from the output terminal OUT of the operational amplifiers OP1. A current supply part 51 supplies a current having the same amount as a current flowing between the output terminals OUT of the operational amplifiers OP1, OP2 and having reverse polarity to the output terminal OUT of the operational amplifier OP1. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：减少通过两个电阻器连接两个运算放大器的输出端子来配置的电压加法器电路的运算结果误差。 解决方案：电压加法器电路50包括插入在运算放大器OP1，OP2的输出端子OUT之间的两个运算放大器OP1，OP2和电阻器ra，rb。 电压Va，Vb被施加到运算放大器OP1，OP2的各个正相输入端IN +，并且从运算放大器OP1的输出端OUT输出电压Va，Vb被加权相加的电压Vo。 电流供给部分51提供具有与在运算放大器OP1，OP2的输出端子OUT之间流动并具有与运算放大器OP1的输出端子OUT具有相反极性的电流相同量的电流。 版权所有（C）2011，JPO＆INPIT