公开(公告)号：JPH08335398A

公开(公告)日：1996-12-17

申请号：JP16300995

申请日：1995-06-06

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C17/18

Abstract: PURPOSE: To provide a semiconductor memory of a clock synchronizing system in which high sped access can be performed by shortening the time required for selecting a word line. CONSTITUTION: A row decoder 102 selecting a word line has a pre-decoder 31 which decodes a row address in addresses taken in by an address buffer and obtains plural word line driving signals. Further, the row decoder 102 has latches 32a, 32b of two systems which make a word line driving signal of a row address successively obtained in synchronism with a clock, takes in them alternately, and hold them, and a selector 33 which makes word line driving signals held by them synchronize with a clock, takes out them alternately, and supplies them to a word line WL. By making circuit constitution like this, a clock cycle is not limited by a time from address latch in an address buffer to data latch in a sense amplifier.

公开(公告)号：JPH08185698A

公开(公告)日：1996-07-16

申请号：JP33963194

申请日：1994-12-28

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN

IPC: G11C17/00 ,  G11C11/41 ,  G11C16/06

Abstract: PURPOSE: To make possible a high-speed access without accompanying the increasing of current consumption by making a device a bit line precharging system precharging only a bit line selected by a next address. CONSTITUTION: This device has a memory cell array 1, an address buffer 2, a column decoder 4, a row decoder 3 and a sense-amplifier 6 and the address buffer 2 has two systems of clock cyclic address registers whose input terminals are commonly connected and fetching addresses in time-division manner. A next address judging circuit 10 judges whether address data of consecutive timing held in two systems of address registers of the address buffer 2 are different or same. A bit line charging means is consisting of the column decoder for a precharge 11, the column selector for the precharge 12 and a bias circuit 13 and selectively precharges only the bit line of an address to be next accessed whilst the means performs the reading of certain data based on the judged result of the next address judging circuit 10.

公开(公告)号：JP2009027757A

公开(公告)日：2009-02-05

申请号：JP2008282891

申请日：2008-11-04

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KAWAI HIROKATA ,  TSUJI NOBUAKI ,  TANAKA TAISHIN

IPC: H04B1/713 ,  H04B1/7136 ,  H04B1/7143

Abstract: PROBLEM TO BE SOLVED: To surely reduce unnecessary electromagnetic radiation by a simple configuration.
SOLUTION: A control part 20 generates specification signals C11-C52 for selecting frequencies different from previously-specified frequencies from a plurality of frequencies in a predetermined order to specify all of the plurality of frequencies in a single sequence. A signal generating part 10 is provided with current supply units U1-U5, and charges and discharges a certain amount of a current to a capacitance element 12 to generate a triangular wave TRI. A comparison circuit 13 compares the triangular wave TRI with an upper limit voltage ULMT and a lower limit voltage DLMT. Based on the comparison result, a clock signal generating circuit 14 generates a first clock signal CK1 and a second clock signal CK2.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：通过简单的配置可靠地减少不必要的电磁辐射。 解决方案：控制部分20产生用于以预定顺序从多个频率中选择与先前指定的频率不同的频率的指定信号C11-C52，以指定单个序列中的所有多个频率。 信号发生部10设置有电流供给部U1〜U5，对电容元件12进行一定量的电流的充放电，生成三角波TRI。 比较电路13将三角波TRI与上限电压ULMT和下限电压DLMT进行比较。 基于比较结果，时钟信号发生电路14产生第一时钟信号CK1和第二时钟信号CK2。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008017336A

公开(公告)日：2008-01-24

申请号：JP2006188374

申请日：2006-07-07

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： TANAKA TAISHIN ,  TSUJI NOBUAKI ,  KAWAI HIROKATA

IPC: H03F3/34 ,  H03F1/00 ,  H03F3/181 ,  H04R3/00

Abstract: PROBLEM TO BE SOLVED: To provide an amplifier capable of accurately canceling the offset voltage.
SOLUTION: The amplifier 1 comprises a circuit 2 at an input stage and an amplifying section 10. The offset voltage Vos, generated by an operational amplifier OP2, is canceled by controlling voltage generated by an offset voltage cancellation circuit 12 by a logic circuit 11. The offset voltage cancelation circuit 12 comprises a resistor, a first current source connected to one end of the resistor, and a second current source connected to the other end, and the value of current flowing into the resistor from the first current source is made to coincide with that of current flowing to the second current source from the resistor, thus making the voltage for canceling the offset at both the ends of the resistor generated. In this case, the current is prevented from flowing into a circuit connected to both the ends of the resistor, thus canceling the offset voltage without affecting the operation of the circuit.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供能够精确地抵消偏移电压的放大器。 解决方案：放大器1包括在输入级的电路2和放大部分10.由运算放大器OP2产生的偏移电压Vos通过将偏移电压消除电路12产生的电压控制为逻辑 偏移电压消除电路12包括电阻器，连接到电阻器的一端的第一电流源和连接到另一端的第二电流源，以及从第一电流源流入电阻器的电流值 使其与从电阻器流到第二电流源的电流一致，从而产生用于抵消所产生的电阻器两端的偏移的电压。 在这种情况下，防止电流流入连接到电阻器的两端的电路，从而抵消偏移电压而不影响电路的操作。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008017320A

公开(公告)日：2008-01-24

申请号：JP2006188303

申请日：2006-07-07

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KAWAI HIROKATA ,  TSUJI NOBUAKI ,  TANAKA TAISHIN

IPC: H03F1/52 ,  H03F3/45

Abstract: PROBLEM TO BE SOLVED: To control a signal according to temperature without deteriorating the output signal of a limiter circuit. SOLUTION: When the temperature of a circuit is less than reference temperature, a differential amplifier 400 functions as the amplifier of a voltage follower, thus outputting a control voltage Vp applied to a PLMT terminal as a limiter voltage Vo as it is. When the temperature of the circuit becomes not less than the reference temperature, the differential amplifier 400 functions as a differential amplifier, where the potential of an input signal reaches potential DIN of a node N1 and potential V12' of a node N3. In this case, by the characteristics of the potential DIN decreasing at a fixed ratio to temperature rise, the differential amplifier 400 outputs a limiter voltage decreasing at a fixed ratio to the temperature rise. Therefore, since the limiter voltage Vo does not change rapidly, the output signal of the limiter circuit 500 does not deteriorate. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：根据温度控制信号，而不会使限幅器电路的输出信号恶化。 解决方案：当电路的温度小于参考温度时，差分放大器400用作电压跟随器的放大器，从而输出施加到PLMT端子的控制电压Vp作为限幅器电压Vo。 当电路温度不低于参考温度时，差分放大器400用作差分放大器，其中输入信号的电位达到节点N1的电位DIN和节点N3的电位V12'。 在这种情况下，差分放大器400通过固定比率与温度上升而降低的电位DIN的特性，输出以固定比例降低到温度上升的限幅电压。 因此，由于限幅电压Vo不会迅速变化，所以限幅电路500的输出信号不会变差。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2003125806A

公开(公告)日：2003-05-07

申请号：JP2001329745

申请日：2001-10-26

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN

IPC: A63B71/06 ,  A43B23/24 ,  G10H1/00 ,  G10H1/34

Abstract: PROBLEM TO BE SOLVED: To provide an electronic-sound generating shoe which generates various kinds of sound by walking or running to increase pleasure of walking or running. SOLUTION: A speaker 1 is equipped on the upper face of this electronic- sound generating shoe and a pressure sensor 2 on the toe part on the backside of the shoe and a pressure sensor 3 on the heel part on the backside of the shoe. A control unit 4 is equipped on a side part of the shoe. When a user set a number on a number setting device by switches T1, T2, a tone corresponding to the set number is set in the sound source circuit inside. When a user walks wearing the shoe, pressure is applied on the pressure sensors 2, 3. When pressure applied on the pressure sensor exceeds a prescribed value, a signal is outputted to the sound source circuit and a sound signal is formed in the sound source circuit and outputted to the speaker 1.

公开(公告)号：JPH10199280A

公开(公告)日：1998-07-31

申请号：JP35044996

申请日：1996-12-27

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN

IPC: G11C16/04 ,  G11C16/06

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device whose malfunctioning caused by the influence of the noise and the word line delay can be avoided. SOLUTION: A memory cell array 1 has bit lines BL and word lines WL which cross each other and NAND-type memory cells MC in which binary data selected by the bit lines BL and the word lines WL are written in a nonvolatile manner. Dummy cells DM which have larger resistances than the memory cells are connected to the one side ends of the respective bit lines BL. Four memory cells MC which are driven in common by the word lines WL are are connected two by two to the bit lines BL1 and BL2 through 4-stage selection gates S11, S12,..., S44. The cells are so driven as to have one of the bit lines BL1 and BL2 in a non-selective state when the other is in a selective state. The data sensing is performed by a differential sensing amplifier by using the bit line in the non-selective state as a dummy bit line.

公开(公告)号：JPH10117138A

公开(公告)日：1998-05-06

申请号：JP15138697

申请日：1997-06-09

Applicant: YAMAHA CORP

Inventor： SHICHIMIYA NORITOMO ,  TANAKA TAISHIN

IPC: G01R19/165 ,  G05F3/24 ,  G11C11/4074 ,  H01L21/822 ,  H01L27/04 ,  H03K5/13 ,  H03K19/00 ,  H03K19/0175 ,  H03K5/14

Abstract: PROBLEM TO BE SOLVED: To provide the semiconductor integrated circuit that enhances its capability independently of a power supply voltage and is manufactured at a low cost. SOLUTION: A power supply voltage detection circuit provided to the semiconductor integrated circuit provides an output of a high level signal from its node S1 when a power supply voltage of the IC is lower than a prescribed voltage and provides an output of a low level signal from its node S1 when the power supply voltage of the IC is higher than the prescribed voltage. Then the output signal of the node S1 is used for a control signal to select the number of stages of a timing compensation delay circuit that makes a drive sequence of each circuit in the semiconductor integrated circuit proper thereby realizing the semiconductor integrated circuit that fulfills a prescribed function over a wide operating power supply voltage range and is manufactured at a low cost.

公开(公告)号：JPH0935490A

公开(公告)日：1997-02-07

申请号：JP20288695

申请日：1995-07-17

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN

IPC: G11C17/12

Abstract: PROBLEM TO BE SOLVED: To obtain a semiconductor memory in which the noise resistance is enhanced without sacrifice of high speed performance. SOLUTION: In a mask ROM arranged with bit lines BLi and word lines WLj crossing each other where memory cells MCij being driven through a select word line are arranged along each bit line BLi and a data is written fixedly in each memory cell MCij, a dummy bit line DBLi is arranged in parallel with each bit line BLi while being paired therewith. Each dummy bit line DBLi is arranged with dummy cells DCij being written fixedly with a data reverse to that of each memory cell MCij corresponding to that arranged along a paired bit line BLi and driven selectively and simultaneously by a same word line. A differential sense circuit SAi detects the difference of output signal between the bit line BLi and a paired dummy bit line DBLi.

公开(公告)号：JPH07334997A

公开(公告)日：1995-12-22

申请号：JP15030194

申请日：1994-06-08

Applicant: YAMAHA CORP

Inventor： TANAKA TAISHIN

IPC: G11C17/18

Abstract: PURPOSE:To obtain a semiconductor storage device which can reduce noise in power supply line and can surely prevent malfunction. CONSTITUTION:This device is provided with a sense amplifier column 5 which has a memory cell array 1, an address buffer 1, a row decoder 3, and a column decoder 4, and reads out selected plural bit data of the memory cell array 1 in parallel and an output buffer column 7. An output delay circuit column 6 consisting of plural output delay circuits Ti for delaying output signals of each sense amplifier SAi with different delay times respectively is provided between the sense amplifier column 5 and the output buffer column 7, and rising timing and falling timing of parallel output are shifted to each other. Thereby, a power supply noise is reduced.