公开(公告)号：WO1996023364A1

公开(公告)日：1996-08-01

申请号：PCT/US1995012566

申请日：1995-10-12

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  CORRY, Alan, G. ,  PURI, Manoj ,  SUTHERLAND, Robert, A.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: H04B01/10

CPC classification number: G06K9/0057 ,  G06K9/0051

Abstract: An apparatus and method for decorrelating pairs of mutually contaminated channels in a multi-channel digital signal including two identical data processing paths and a feedback path. Each pair of mutually contaminated channels consists of a first contamined channel and a second contaminated channel. Initially, first and second shifted signals are generated by shifting the original contaminated signal such that the first shifted signal has the first contaminated channel centered at zero frequency and the second shifted signal has the second contaminated channel centered at zero frequency. Each of the first and second shifted signals are coupled to one of the two identical signal processing paths. The first path generates an error corruption component corresponding to the first shifted input signal and subtracts this corruption component from the second shifted signal in order to generate a third decorrelated digital signal. The second path generates an error corruption component corresponding to the second shifted input signal and subtracts it from the first shifted signal in order to generate a fourth decorrelated digital signal. The feedback path generates a current average error correlation factor by multiplying the third and fourth to generate an instantaneous error factor and summing this with the previous average error correlation factor for all samples. The current average error correlation factor is used to generate the first and second error corruption components. Each of the corrupted channels in the original contamined digital signal are decorrelated when the third and fourth digital signals are decorrelated.

Abstract translation: 一种用于在包括两个相同的数据处理路径和反馈路径的多通道数字信号中去相互关联相互污染的通道的装置和方法。 每对相互污染的通道由第一被检测通道和第二污染通道组成。 首先，通过移动原始污染信号来产生第一和第二移位信号，使得第一移位信号具有以零频率为中心的第一污染信道，并且第二移位信号具有以零频率为中心的第二污染信道。 第一和第二移位信号中的每一个耦合到两个相同的信号处理路径之一。 第一路径产生与第一移位输入信号对应的错误损坏部件，并从第二移位信号中减去该损坏部件，以产生第三解相关数字信号。 第二路径产生与第二移位输入信号对应的错误损坏部件，并将其从第一移位信号中减去，以产生第四解相关数字信号。 反馈路径通过乘以第三和第四来产生当前平均误差相关因子以产生瞬时误差因子，并将其与所有样本的先前平均误差相关因子相加。 当前的平均误差相关因子用于产生第一和第二错误损坏组件。 当第三和第四数字信号被去相关时，原始被检查的数字信号中的每个被破坏的信道都被去相关。

公开(公告)号：WO1996003750A1

公开(公告)日：1996-02-08

申请号：PCT/US1995009366

申请日：1995-07-25

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  BATEMAN, Bruce, L.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G11C05/14

CPC classification number: G11C5/143 ,  G11C7/062

Abstract: A circuit for protecting an interconnect line from certain undesirable voltage swings for a given input signal. A transmission gate is coupled in series between the input signal and the interconnect line. The transmission gate's input terminal is coupled to the input signal, its output terminal is coupled to the interconnect line, and its control terminal is coupled to the output of an inverter. The input of the inverter is coupled to the input signal. When the input signal transitions to a voltage that exceeds the trip point of the inverter, the inverter outputs a signal that disables the transmission gate such that the node is isolated from the input signal. A PFET transmission gate is utilized for protection against voltages that are too negative, and an NFET transmission gate is utilized for protection against voltages that are too positive. The inverter may be replaced by a comparator having its positive input coupled to a reference voltage and its negative input coupled to the input signal. The reference voltage determines the trip point of the protection circuit. The protection circuit may also include first and second biased MOS devices (having different channel types) coupled between first and second working potentials. The gate of the first MOS device is coupled to the input signal and the gate of the second MOS device is coupled to the output of the inverter. The MOS devices function as a conductive voltage divider network to establish a voltage on the node when the node is isolated from the input signal.

Abstract translation: 用于保护互连线免于给定输入信号的某些不期望的电压摆动的电路。 传输门串联在输入信号和互连线之间。 传输门的输入端耦合到输入信号，其输出端耦合到互连线，其控制端耦合到逆变器的输出。 反相器的输入耦合到输入信号。 当输入信号转换到超过变频器跳闸点的电压时，变频器输出禁止传输门的信号，使得节点与输入信号隔离。 PFET传输门用于防止太负电压的保护，并且NFET传输门被用于防止过大的电压。 反相器可以由比较器代替，其比较器的正输入耦合到参考电压，其负输入耦合到输入信号。 参考电压确定保护电路的跳变点。 保护电路还可以包括耦合在第一和第二工作电位之间的第一和第二偏置MOS器件（具有不同的沟道类型）。 第一MOS器件的栅极耦合到输入信号，第二MOS器件的栅极耦合到反相器的输出端。 MOS器件用作导电分压器网络，以在节点与输入信号隔离时在节点上建立电压。

公开(公告)号：WO1995005033A1

公开(公告)日：1995-02-16

申请号：PCT/US1994004613

申请日：1994-04-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  WONG, Ban, Pak

IPC: H03K19/018

CPC classification number: H03K19/017563 ,  H03K19/013 ,  H03K19/01831

Abstract: An apparatus for reducing transmisson delay times when transmitting differential signals in an integrated circuit along long interconnect lines (10, 11) includes a current mode line driver which converts the differential signal to be transmitted into a signal that has a relatively low peak-to-peak voltage and large differential current changes. A receiver responsive to differential current changes converts the signal back into an output differential signal having peak-to-peak voltages adaptable to subsequent logic stages. A feedback circuit (Q5, Q6) coupled to the interconnect lines (10, 11) and the receiver functions to clamp the interconnect lines (10, 11) to a predetermined voltage while allowing the output differential signal to have peak-to-peak voltages greater than the predetermined voltage.

Abstract translation: 一种用于在沿着长互连线（10,11）的集成电路中传输差分信号时减小透射延迟时间的装置包括：电流模式线驱动器，其将待传输的差分信号转换成具有相对低的峰 - 峰值电压和大差分电流变化。 响应于差分电流变化的接收器将信号反馈回具有适应于后续逻辑级的峰 - 峰电压的输出差分信号。 耦合到互连线（10,11）的反馈电路（Q5，Q6）和接收器用于将互连线（10,11）钳位到预定电压，同时允许输出差分信号具有峰 - 峰电压 大于预定电压。

公开(公告)号：WO1994005085A1

公开(公告)日：1994-03-03

申请号：PCT/US1993005106

申请日：1993-05-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  WONG, Ban, Pak

IPC: H03K19/0944

CPC classification number: H03K19/018521 ,  H03K19/00361 ,  H03K19/0136 ,  H03K19/017518

Abstract: An ECL-to-CMOS level translator and BiCMOS buffer are described. The current supplied from the first input PMOS transistor (P1) is the input current to a current mirror comprising the first and second NMOS transistors (N1 and N2). The current mirror controls the current sourcing and sinking capability of the translator. Third and fourth NMOS transistors (N3 and N4) are coupled to the first and second NMOS transistors in the current mirror and function to vary the source-to-body voltage of the first and second NMOS transistors and consequently their gain which results in increased current drive and sinking capability. The BiCMOS differential buffer of the present invention provides a differential output signal on first and second output nodes (115 and 215). It is comprised of first and second cross-coupled buffers (100B and 200B). Cross-coupling the buffers results in improved high-to-low transition times.

Abstract translation: 描述了ECL到CMOS电平转换器和BiCMOS缓冲器。 从第一输入PMOS晶体管（P1）提供的电流是包括第一和第二NMOS晶体管（N1和N2）的电流镜的输入电流。 当前镜像控制翻译器的当前采样和下载功能。 第三和第四NMOS晶体管（N3和N4）耦合到电流镜中的第一和第二NMOS晶体管，并且用于改变第一和第二NMOS晶体管的源极体电压，并因此改变其增益，从而导致电流增加 驱动和下沉能力。 本发明的BiCMOS差分缓冲器在第一和第二输出节点（115和215）上提供差分输出信号。 它由第一和第二交叉耦合缓冲器（100B和200B）组成。 交叉耦合缓冲区导致改进的高到低的转换时间。

公开(公告)号：WO1993017498A1

公开(公告)日：1993-09-02

申请号：PCT/US1993001894

申请日：1993-02-23

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  ROSSEEL, Geert ,  HERNDON, William, H. ,  MATTHEWS, James, A.

IPC: H03K17/16

CPC classification number: H03K19/086 ,  H03K17/14 ,  H03K17/567 ,  H03K17/603 ,  H03K19/09448

Abstract: An improved BiCMOS logic circuit (70) utilizes an emitter-coupled pair of bipolar transistors (21, 22) for differentially comparing an input signal (Vin) with a logic reference level (VBIAS). Each of the bipolar transistors are resistively loaded by a network of p-channel metal-oxide-semiconductor (PMOS) transistors (26, 27) coupled in parallel. At least one of the parallel combination of transistors has its gate coupled to a control signal (VREF2) providing a variable load resistance. The control signal is preferably provided by a feedback network (52, 53) which maintains a constant voltage swing across the network over temperature.

Abstract translation: 改进的BiCMOS逻辑电路（70）利用发射极耦合的双极晶体管（21,22）来差分地比较输入信号（Vin）与逻辑参考电平（VBIAS）。 每个双极晶体管由并联耦合的p沟道金属氧化物半导体（PMOS）晶体管（26,27）的网络进行电阻负载。 晶体管的并联组合中的至少一个具有耦合到提供可变负载电阻的控制信号（VREF2）的栅极。 控制信号优选地由反馈网络（52,53）提供，反馈网络（52,53）通过温度在网络上保持恒定的电压摆幅。

公开(公告)号：WO1992017745A1

公开(公告)日：1992-10-15

申请号：PCT/US1992002622

申请日：1992-03-31

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: F28F07/02

CPC classification number: F28F3/12 ,  F28D2021/0029 ,  F28F2260/02 ,  H01L23/473 ,  H01L2924/0002 ,  Y10T29/49366 ,  Y10T29/49368 ,  H01L2924/00

Abstract: A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates (10), laminated together to form a block (18). Each plate has a pair of holes (14, 15) cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.

公开(公告)号：WO1991011019A1

公开(公告)日：1991-07-25

申请号：PCT/US1991000211

申请日：1991-01-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: H01L21/225

CPC classification number: H01L21/28211 ,  H01L21/28525 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/136 ,  H01L2924/00

Abstract: A method for forming a BICMOS integrated circuit having MOS field effect transistors and bipolar junction transistors is disclosed. The process comprises first defining separate active areas, forming a gate dielectric layer and a first layer of polysilicon. This polysilicon is then selectively etched to form a plurality of equally-spaced first polysilicon members comprising the gates (33, 34) of the MOS transistors and the extrinsic base contacts (35) of the NPN transistors. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members (65, 66, 67, 68, 69). Impurities are diffused from the polysilicon members to form source/drain regions (73, 74, 75, 76) of the MOS transistors and the extrinsic base (81) and emitter (77) regions of the NPN transistors. The final processing steps include providing the interconnection of the MOS and NPN transistors.

公开(公告)号：WO2016003820A9

公开(公告)日：2016-01-07

申请号：PCT/US2015/038078

申请日：2015-06-26

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： HANSEN, Craig ,  MOUSSOURIS, John ,  MASSALIN, Alexia

IPC: G06F9/30

Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

公开(公告)号：WO1997045772A1

公开(公告)日：1997-12-04

申请号：PCT/US1997008418

申请日：1997-05-27

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  CHEN, J., Fung

IPC: G03F09/00

CPC classification number: G03F1/36 ,  G03F7/70433

Abstract: There is disclosed a photolithography mask and method of making the same that utilizes serifs to increase to correspondence between an actual circuit design and the final circuit pattern on a semiconductor wafer. The mask uses a plurality of serifs having a size determined by a resolution limit of the optical exposure tool used during the fabrication process. The serifs are positioned on the corner regions of the mask such that a portion of surface area for each of the serifs overlaps the corner regions of the mask. The size of the serifs is about one-third the resolution limit of said optical exposure tool. About 33 to about 40 percent of the total surface area of the serifs overlap the corner regions of the mask.

Abstract translation: 公开了一种光刻掩模及其制造方法，其利用衬底来增加实际电路设计和半导体晶片上的最终电路图案之间的对应关系。 掩模使用多个衬线，其具有由在制造过程中使用的光学曝光工具的分辨率极限确定的尺寸。 衬线位于掩模的拐角区域上，使得每个衬线的表面积的一部分与掩模的拐角区域重叠。 衬线的尺寸约为所述光学曝光工具的分辨率极限的三分之一。 衬线的总表面积的约33％至约40％与掩模的拐角区域重叠。

公开(公告)号：WO1997014084A2

公开(公告)日：1997-04-17

申请号：PCT/US1996016297

申请日：1996-10-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  HANSEN, Craig, C.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G06F00/00

CPC classification number: G06F12/0284 ,  G06F12/1045 ,  G06F12/1491

Abstract: A virtual memory system including a local-to-global virtual address translator for translating local virtual addresses having associated task specific address spaces into global virtual addresses corresponding to an address space associated with multiple tasks, and a global virtual-to-physical address translator for translating global virtual addresses to physical addresses. Local-to-global virtual translation is performed by either mapping local virtual addresses to a single global virtual address space or to multiple global virtual address spaces. The local-to-global virtual translator includes a cell which corresponds to each local address space for performing the translations. Separate cache and tag structures are employed for handling data and instruction memory accesses. The cache can be configured into a buffer portion or a cache portion for faster cache accesses. Protection information is provided by each of the local virtual-to-global virtual address translator, the global virtual-to-physical address translator, the cache tag storage, or a protection information buffer depending on whether a cache hit, cache miss, or buffer access occurs during a given data or instruction access. Memory area privilege protection is also achieved by employing a gateway instruction which generates an address to access a gateway storage area.

Abstract translation: 一种包括本地到全局虚拟地址转换器的虚拟存储器系统，用于将具有相关联的任务特定地址空间的本地虚拟地址转换成对应于与多个任务相关联的地址空间的全局虚拟地址，以及全局虚拟到物理地址转换器， 将全局虚拟地址转换为物理地址。 通过将本地虚拟地址映射到单个全局虚拟地址空间或多个全局虚拟地址空间来执行本地到全局虚拟转换。 本地到全球的虚拟翻译器包括对应于用于执行翻译的每个本地地址空间的单元。 采用独立的缓存和标签结构来处理数据和指令存储器访问。 高速缓存可以被配置成缓冲部分或高速缓存部分，以便更快的高速缓存访​​问。 保护信息由本地虚拟到全局虚拟地址转换器，全球虚拟到物理地址转换器，高速缓存标签存储器或保护信息缓冲器中的每一个提供，取决于缓存命中，高速缓存未命中或缓冲器 在给定的数据或指令访问期间进行访问。 存储区域特权保护也可以通过采用生成访问网关存储区域的地址的网关指令来实现。