-
21.发明申请TWO-STEP METHOD FOR JOINING A SEMICONDUCTOR TO A SUBSTRATE WITH CONNECTING MATERIAL BASED ON SILVER 审中-公开将半导体接合到具有基于银的连接材料的基板的两步法公开(公告)号：US20150123263A1
公开(公告)日：2015-05-07
申请号：US14400121
申请日：2013-04-02
Applicant: Robert Bosch GmbH
Inventor： Christiane Frueh , Michael Guenther , Thomas Herboth
IPC: H01L23/00
CPC classification number: H01L24/83 , H01L24/27 , H01L24/29 , H01L24/32 , H01L2224/2731 , H01L2224/2732 , H01L2224/27442 , H01L2224/27505 , H01L2224/27901 , H01L2224/29082 , H01L2224/29083 , H01L2224/29339 , H01L2224/32225 , H01L2224/75315 , H01L2224/831 , H01L2224/83192 , H01L2224/83203 , H01L2224/83208 , H01L2224/8384 , H01L2924/01047 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/15747 , H01L2924/201 , H01L2924/20101 , H01L2924/20102 , H01L2924/20103 , H01L2924/20104 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20108 , H01L2924/20109 , H01L2924/2011 , H01L2924/20111 , H01L2924/00
Abstract: The invention relates to a method for joining a semiconductor (20) to a substrate (10), comprising the following steps: •applying a first paste layer (1) of a sintering paste to the substrate; •heating and compressing the first paste layer to form a first sintered layer; •applying a second paste layer (2) of a sintering paste to the first sintered layer and arranging a semiconductor (20) on the second paste layer; •heating and compressing the second paste layer (2) to form a second sintered layer. The invention further relates to a semiconductor component produced by means of the method.
Abstract translation: 本发明涉及将半导体（20）接合到基板（10）的方法，包括以下步骤：将烧结糊的第一糊剂层（1）施加到基底上; 加热和压缩第一浆料层以形成第一烧结层; 将烧结膏的第二浆料层（2）施加到所述第一烧结层并将半导体（20）布置在所述第二糊料层上; 加热和压缩第二浆料层（2）以形成第二烧结层。 本发明还涉及通过该方法制造的半导体部件。
-
22.发明授权公开(公告)号：US09536854B2
公开(公告)日：2017-01-03
申请号：US14893833
申请日：2015-03-31
Inventor： Takashi Yamada , Daizo Oda , Ryo Oishi , Teruo Haibara , Tomohiro Uno
IPC: H01B5/00 , H01L23/00 , B21C1/00 , C22C5/06 , C22C5/08 , C22F1/00 , C22F1/14 , B23K35/30 , B23K35/02
CPC classification number: H01L24/45 , B21C1/00 , B21C1/003 , B23K35/0227 , B23K35/3006 , C22C5/06 , C22C5/08 , C22F1/00 , C22F1/14 , H01L24/43 , H01L2224/4321 , H01L2224/43848 , H01L2224/45012 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45664 , H01L2924/00011 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/013 , H01L2924/10253 , H01L2924/201 , H01L2924/20108 , H01L2924/20109 , H01L2924/2011 , H01L2924/20111 , H01L2924/01049 , H01L2924/01045 , H01L2924/00014 , H01L2924/01005 , H01L2924/01016 , H01L2924/01017 , H01L2924/00015 , H01L2924/01201
Abstract: Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis “a” and a short axis “b” of 10 or more and with an area of 15 μm2 or more (“fiber texture”), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%. During the drawing step, a drawing operation with a rate of reduction of area of 15.5% or more is performed at least once. The final heat treatment temperature and the pre-final heat treatment temperature are made predetermined ranges.
Abstract translation: 用于半导体器件的接合线，其中通过（1）在包含线中心并且平行于线纵向（线中心横截面）的横截面中抑制倾斜故障和弹簧故障，不存在具有 长轴“a”的比率a / b和短轴“b”为10以上，面积为15μm2以上（“纤维织构”），（2）当测定线材纵向的晶体方向 在线中心横截面的方向上，相对于线纵向的角度差为15°以下的晶体方向<100>的面积比为50％〜90％，（3）当 在线表面测定线长方向的晶体方向，晶体方向<100>与线长度方向的角度差为15°以下的面积比为50％〜90％。 在拉伸步骤中，至少进行一次具有15.5％以上的面积减小率的拉拔操作。 将最终的热处理温度和预热处理温度设定为预定范围。
-
公开(公告)号：US20160204078A1
公开(公告)日：2016-07-14
申请号：US14596861
申请日：2015-01-14
Applicant: International Business Machines Corporation
Inventor： Stephen W. Bedell , Cheng-Wei Cheng , Keith E. Fogel , Ning Li , Devendra K. Sadana
CPC classification number: H01L24/83 , B32B37/28 , B32B2457/14 , H01L2224/83002 , H01L2224/83047 , H01L2224/83095 , H01L2224/83888 , H01L2924/01028 , H01L2924/201
Abstract: A first substrate including a radius of curvature and a stressor layer is first provided. An outermost bowed, e.g., curved, surface of the first substrate is then brought into intimate contact with a surface of a second substrate. Bonding of the entirety of the first substrate to the second substrate is then achieved by reducing the radius of curvature of the first substrate by controlling the temperature at which bonding occurs.
Abstract translation: 首先提供包括曲率半径和应力层的第一衬底。 然后使第一基底的最外面的弯曲的，例如弯曲的表面与第二基底的表面紧密接触。 然后通过控制发生接合的温度来减小第一衬底的整体的第二衬底的接合，从而减小第一衬底的曲率半径。
-
24.发明申请公开(公告)号：US20160111389A1
公开(公告)日：2016-04-21
申请号：US14893833
申请日：2015-03-31
Inventor： Takashi YAMADA , Daizo ODA , Ryo OISHI , Teruo HAIBARA , Tomohiro UNO
CPC classification number: H01L24/45 , B21C1/00 , B21C1/003 , B23K35/0227 , B23K35/3006 , C22C5/06 , C22C5/08 , C22F1/00 , C22F1/14 , H01L24/43 , H01L2224/4321 , H01L2224/43848 , H01L2224/45012 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45664 , H01L2924/00011 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/013 , H01L2924/10253 , H01L2924/201 , H01L2924/20108 , H01L2924/20109 , H01L2924/2011 , H01L2924/20111 , H01L2924/01049 , H01L2924/01045 , H01L2924/00014 , H01L2924/01005 , H01L2924/01016 , H01L2924/01017 , H01L2924/00015 , H01L2924/01201
Abstract: Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis “a” and a short axis “b” of 10 or more and with an area of 15 μm2 or more (“fiber texture”), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%. During the drawing step, a drawing operation with a rate of reduction of area of 15.5% or more is performed at least once. The final heat treatment temperature and the pre-final heat treatment temperature are made predetermined ranges.
Abstract translation: 用于半导体器件的接合线，其中通过（1）在包含线中心并且平行于线纵向（线中心横截面）的横截面中抑制倾斜故障和弹簧故障，不存在具有 长轴“a”的比率a / b和短轴“b”为10以上，面积为15μm2以上（“纤维织构”），（2）当测定线材纵向的晶体方向 在线中心横截面的方向上，相对于线纵向的角度差为15°以下的晶体方向<100>的面积比为50％〜90％，（3）当 在线表面测定线长方向的晶体方向，晶体方向<100>与线长度方向的角度差为15°以下的面积比为50％〜90％。 在拉伸步骤中，至少进行一次具有15.5％以上的面积减小率的拉拔操作。 将最终的热处理温度和预热处理温度设定为预定范围。
-
25.发明授权GaN transistor with improved bonding pad structure and method of fabricating the same 有权具有改进的焊盘结构的GaN晶体管及其制造方法公开(公告)号：US09165896B2
公开(公告)日：2015-10-20
申请号：US14453969
申请日：2014-08-07
Inventor： Hae Cheon Kim , Ho Kyun Ahn , Byoung Gue Min , Hyung Sup Yoon , Jong Won Lim
CPC classification number: H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/0225 , H01L2224/03466 , H01L2224/03848 , H01L2224/0401 , H01L2224/04042 , H01L2224/05083 , H01L2224/05084 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05644 , H01L2224/48463 , H01L2924/00014 , H01L2924/10158 , H01L2924/1033 , H01L2924/1304 , H01L2924/13091 , H01L2924/1423 , H01L2924/201 , H01L2924/37001 , H01L2224/45099
Abstract: The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.
Abstract translation: 本发明涉及一种GaN晶体管及其制造方法，其中通过在源极，漏极和栅极的焊盘的边缘处形成欧姆金属层来改善焊盘的结构，因此 适于引线接合或背面通孔形成工艺。 因此，通过在制造GaN晶体管期间在焊盘的边缘处形成欧姆金属，可以增强焊盘的金属层与GaN基板之间的粘合力， 接合或背面通孔形成工艺，并提高器件的可靠性。
-
Patent Agency Ranking
26.发明授权Glass/ceramics replacement of epoxy for high temperature hermetically sealed non-axial electronic packages 有权玻璃/陶瓷替代环氧树脂用于高温气密密封的非轴向电子封装公开(公告)号：US09111869B2
公开(公告)日：2015-08-18
申请号：US13194585
申请日：2011-07-29
Applicant: Victor Hugo Cruz , David Francis Courtney
Inventor： Victor Hugo Cruz , David Francis Courtney
IPC: H01L29/12 , H01L23/495 , H01L23/29 , H01L23/00 , H01L23/31
CPC classification number: H01L23/291 , H01L23/3107 , H01L23/49513 , H01L23/49524 , H01L23/49541 , H01L23/49562 , H01L23/49582 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/34 , H01L24/36 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/97 , H01L2224/04026 , H01L2224/04042 , H01L2224/05639 , H01L2224/05655 , H01L2224/06181 , H01L2224/29139 , H01L2224/29147 , H01L2224/32245 , H01L2224/37184 , H01L2224/37639 , H01L2224/37655 , H01L2224/40247 , H01L2224/45124 , H01L2224/45139 , H01L2224/48247 , H01L2224/4847 , H01L2224/48699 , H01L2224/48739 , H01L2224/48755 , H01L2224/83439 , H01L2224/83455 , H01L2224/83801 , H01L2224/84801 , H01L2224/85439 , H01L2224/85455 , H01L2224/92246 , H01L2224/92247 , H01L2224/97 , H01L2924/00011 , H01L2924/01029 , H01L2924/0103 , H01L2924/01047 , H01L2924/097 , H01L2924/10253 , H01L2924/10272 , H01L2924/10329 , H01L2924/1033 , H01L2924/15747 , H01L2924/15787 , H01L2924/17738 , H01L2924/181 , H01L2924/186 , H01L2924/201 , H01L2924/20111 , H01L2224/84 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2924/01049 , H01L2924/00014 , H01L2924/01005
Abstract: A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch.
Abstract translation: 用于非轴向电子器件的高温非空腔封装是使用玻璃陶瓷化合物设计的，其能够在高于300-400℃的温度下连续组装和操作。金属钎焊，例如银，银胶体或 铜，用于连接半导体管芯，引线框架和连接器。 这些部件也是热匹配的，使得封装可以在高温下连续地组装和操作，并且可承受极端的温度变化，而不会发生键失效或者由于热失配引起的封装破裂。
-
公开(公告)号：JPWO2015152191A1
公开(公告)日：2017-04-13
申请号：JP2015516369
申请日：2015-03-31
Applicant: 日鉄住金マイクロメタル株式会社 , 新日鉄住金マテリアルズ株式会社
IPC: H01L21/60
CPC classification number: H01L24/45 , B21C1/00 , B21C1/003 , B23K35/0227 , B23K35/3006 , C22C5/06 , C22C5/08 , C22F1/00 , C22F1/14 , H01L24/43 , H01L2224/4321 , H01L2224/43848 , H01L2224/45012 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/45664 , H01L2924/00011 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/013 , H01L2924/201 , H01L2924/20108 , H01L2924/20109 , H01L2924/2011 , H01L2924/20111 , H01L2924/01049 , H01L2924/01045 , H01L2924/00 , H01L2924/00014 , H01L2924/01005
Abstract: リーニング不良とスプリング不良をともに抑制するため、(1)ワイヤ中心を含みワイヤ長手方向に平行な断面(ワイヤ中心断面)において、長径aと短径bの比a/bが10以上でありさらに面積が15μm2以上である結晶粒(繊維状組織)が存在せず、(2)ワイヤ中心断面における、ワイヤ長手方向の結晶方位を測定した結果、前記ワイヤ長手方向に対して角度差が15°以下である結晶方位 の存在比率が面積率で50%以上90%以下であり、(3)ワイヤ表面における、ワイヤ長手方向の結晶方位を測定した結果、前記ワイヤ長手方向に対して角度差が15°以下である結晶方位 の存在比率が面積率で50%以上90%以下であることを特徴とする半導体装置用ボンディングワイヤ。伸線工程中に減面率が15.5%以上の伸線加工を少なくとも1回行い、最終熱処理温度と最終前熱処理温度を所定範囲とする。
-
公开(公告)号：US09972597B2
公开(公告)日：2018-05-15
申请号：US14800613
申请日：2015-07-15
Applicant: HYUNDAI MOTOR COMPANY
Inventor： Kyoung-Kook Hong , Hyun Woo Noh , Youngkyun Jung , Dae Hwan Chun , Jong Seok Lee , Su Bin Kang
IPC: B23K31/00 , B23K35/00 , H01L23/00 , B23K35/02 , B23K35/26 , B23K35/30 , B23K20/02 , B23K20/16 , B23K20/233 , H05K3/34 , B23K101/42 , B23K103/16
CPC classification number: H01L24/83 , B23K20/026 , B23K20/16 , B23K20/233 , B23K35/025 , B23K35/264 , B23K35/3006 , B23K2101/42 , B23K2103/166 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L2224/13294 , H01L2224/13313 , H01L2224/13339 , H01L2224/16227 , H01L2224/16505 , H01L2224/29294 , H01L2224/29313 , H01L2224/29339 , H01L2224/32227 , H01L2224/32505 , H01L2224/81191 , H01L2224/81192 , H01L2224/81825 , H01L2224/8184 , H01L2224/83191 , H01L2224/83192 , H01L2224/83825 , H01L2224/8384 , H01L2924/00015 , H01L2924/10272 , H01L2924/201 , H01L2924/2075 , H01L2924/20751 , H05K3/341 , H05K3/3463 , H05K2201/10166 , H05K2203/1131 , H01L2224/29388 , H01L2924/00014 , H01L2224/13388 , H01L2924/00012
Abstract: A method for bonding with a silver paste includes coating a semiconductor device or a substrate with the silver paste. The silver paste contains a plurality of silver particles and a plurality of bismuth particles. The method further includes disposing the semiconductor on the substrate and forming a bonding layer by heating the silver paste, wherein the semiconductor and the substrate are bonded to each other by the bonding layer.
-
29.发明授权公开(公告)号：US09620434B1
公开(公告)日：2017-04-11
申请号：US15062893
申请日：2016-03-07
Inventor： Shailesh N. Joshi , Masao Noguchi
IPC: H01L21/00 , H01L23/48 , H05K1/11 , H01L23/373 , H01L23/367 , H01L23/00 , H01L25/065 , H01L25/00
CPC classification number: H01L25/50 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/83 , H01L25/0657 , H01L2224/2732 , H01L2224/27418 , H01L2224/27442 , H01L2224/27462 , H01L2224/27464 , H01L2224/2908 , H01L2224/29083 , H01L2224/29124 , H01L2224/29139 , H01L2224/29147 , H01L2224/29155 , H01L2224/29255 , H01L2224/29294 , H01L2224/29295 , H01L2224/29311 , H01L2224/29324 , H01L2224/29339 , H01L2224/29347 , H01L2224/29355 , H01L2224/3201 , H01L2224/32145 , H01L2224/32225 , H01L2224/32503 , H01L2224/83101 , H01L2224/83193 , H01L2224/83424 , H01L2224/83447 , H01L2224/8381 , H01L2224/83825 , H01L2224/8384 , H01L2924/10272 , H01L2924/201 , H01L2924/20106 , H01L2924/20107 , H01L2924/20108 , H01L2924/3512 , H01L2924/00012 , H01L2924/00014
Abstract: A method of bonding a first substrate to a second substrate includes disposing a first high melting point metal layer onto a first substrate, disposing a first low melting point metal layer onto the first high melting point metal layer, disposing a second high melting point metal layer onto a second substrate, and disposing a second low melting point metal layer onto the second high melting point metal layer. The method further includes applying precursor metal particles onto the first and/or second low melting point metal layers, positioning the first and second low melting point metal layers such that the precursor metal particles contact both the first and second low melting point metal layers, and bonding the first substrate to the second substrate by heating the precursor metal particles and each metal layer to form an intermetallic alloy bonding layer between the first and second substrates.
-
30.发明授权公开(公告)号：US09543266B2
公开(公告)日：2017-01-10
申请号：US14893789
申请日：2015-03-31
Inventor： Takashi Yamada , Daizo Oda , Ryo Oishi , Teruo Haibara , Tomohiro Uno
CPC classification number: H01L24/45 , B21C1/00 , B21C1/003 , C22C5/06 , C22C5/08 , C22F1/00 , C22F1/14 , H01L24/43 , H01L2224/4321 , H01L2224/43848 , H01L2224/43986 , H01L2224/45012 , H01L2224/45015 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2924/00011 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/201 , H01L2924/20108 , H01L2924/20109 , H01L2924/2011 , H01L2924/20111 , H01L2924/00 , H01L2924/01201 , H01L2924/01016 , H01L2924/01017 , H01L2924/20751 , H01L2924/20752 , H01L2924/12044 , H01L2924/00015 , H01L2224/45664 , H01L2924/01049 , H01L2924/01045 , H01L2924/01004 , H01L2924/01005
Abstract: Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis “a” and a short axis “b” of 10 or more and with an area of 15 μm2 or more (“fiber texture”), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 10% to less than 50%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 70% or more. During the drawing step, a drawing operation with a rate of reduction of area of 15.5% or more is performed at least once. The final heat treatment temperature and the pre-final heat treatment temperature are made predetermined ranges.
Abstract translation: 用于半导体器件的接合线，其中通过（1）在包含线中心并且平行于线纵向（线中心横截面）的横截面中抑制倾斜故障和弹簧故障，不存在具有 长轴“a”的比率a / b和短轴“b”为10以上，面积为15μm2以上（“纤维织构”），（2）当测定线材纵向的晶体方向 线中心横截面的方向，晶体方向<100>相对于导线纵向方向的角度差为15°以下的面积比为10％以上且小于50％，（3 ）当在线表面测量线长度方向的晶体方向时，晶体方向<100>与线长度方向的角度差为15°以下的面积比为70％以上 。 在拉伸步骤中，至少进行一次具有15.5％以上的面积减小率的拉拔操作。 将最终的热处理温度和预热处理温度设定为预定范围。
-
-
-
-
-
-
-
-
-
Search Results
81
records
(took 0.025 seconds)
