公开(公告)号：US06211745B1

公开(公告)日：2001-04-03

申请号：US09304443

申请日：1999-05-03

Applicant: Lars Henrik Mucke ,  Christopher Dennis Hull ,  Lars Gustaf Jansson

Inventor： Lars Henrik Mucke ,  Christopher Dennis Hull ,  Lars Gustaf Jansson

IPC: H01L2993

CPC classification number: H03F3/45085 ,  H01L27/0805 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/124 ,  H03B5/1265 ,  H03B2201/0266 ,  H03B2201/0283 ,  H03F1/56 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18

Abstract: A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or “binary” varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region having little or no voltage dependency and having a capacitance equal to a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. The capacitance of the binary capacitor can be changed from C1 to C2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value. A plurality of binary capacitors are configured in a parallel arrangement to produce a digitally controlled capacitor. The digitally controlled capacitor can be used in any integrated circuit requiring a tightly controlled tuned network. One application is a voltage-controlled oscillator (VCO) wherein the center output frequency of the VCO is calibrated by digitally modifying the capacitance of the VCO's digitally controlled capacitor. A means for determining whether the VCO requires calibration and a means for calibrating the center output frequency of the VCO is presented.

Abstract translation: 一种使用MOS-FET器件数字控制集成电路器件的电容的方法和装置。 根据本发明的一个方面，提出了一种一位或“二进制”变容二极管，其中MOS-FET器件的栅极 - 体积电容表现出对其栅极和阱注入区域之间施加的直流电压的依赖性。 二元电容器的电容电压特性具有三个主要区域：（1）具有很小或没有电压依赖性并具有等于C1的第一低电容的电容的第一相对平坦的区域; （2）存在电压依赖性的倾斜区域; 和（3）几乎没有或没有电压依赖性并且电容等于C2的第二较高电容的第二相对平坦的区域。 通过将所施加的直流电压的极性从正值改变为负值，可以将二进制电容器的电容从C1改变为C2。 多个二进制电容器被配置成并联布置以产生数字控制的电容器。 数字控制电容器可用于需要严格控制的调谐网络的任何集成电路中。 一种应用是压控振荡器（VCO），其中VCO的中心输出频率通过数字修改VCO的数字控制电容器的电容来校准。 提出了一种用于确定VCO是否需要校准的装置，以及用于校准VCO的中心输出频率的装置。

公开(公告)号：US5600279A

公开(公告)日：1997-02-04

申请号：US481083

申请日：1995-06-07

Applicant: Kazuhiro Mori

Inventor： Kazuhiro Mori

IPC: H03L7/099 ,  H03B1/00 ,  H03B5/12 ,  H03C3/22

CPC classification number: H03B5/1231 ,  H03B5/1203 ,  H03B5/1243 ,  H03B5/1293 ,  H03B2200/004 ,  H03B2201/0208 ,  H03B2201/0283 ,  H03B2201/03

Abstract: A VCO circuit has a voltage variable capacitance CVD2 connected in series with or in parallel to a condenser C3 connected in series with an inductance L1, which constitutes a resonator of the VCO circuit. An adjustment voltage VD2 is applied to a cathode of the voltage variable capacitance CVD2, such that the relation between a control voltage VD1 and an oscillation frequency f0 of the VCO circuit is electrically adjusted to improve the fabrication yield.

Abstract translation: VCO电路具有与构成VCO电路的谐振器的电感L1串联连接或并联连接的电容器C3的电压可变电容CVD2。 将调整电压VD2施加到电压可变电容CVD2的阴极，使得电压调节VCO电路的控制电压VD1和振荡频率f0之间的关系，以提高制造成品率。

公开(公告)号：US5414308A

公开(公告)日：1995-05-09

申请号：US921889

申请日：1992-07-29

Applicant: I-Shi Lee ,  Tim H. T. Shen ,  Stephen R. M. Huang ,  Judy C. L. Kuo

Inventor： I-Shi Lee ,  Tim H. T. Shen ,  Stephen R. M. Huang ,  Judy C. L. Kuo

IPC: H03B1/00 ,  H03B1/04 ,  H03B5/32 ,  H03L7/00

CPC classification number: H03B1/04 ,  H03B2201/0283 ,  H03B5/32

Abstract: A high frequency clock generator has a plurality of quartz crystals capable of providing various output frequencies coupled to multiple oscillator circuits. The output line from each oscillator circuit is coupled to one or more multiplexers so that the user can select one or more output frequencies at the same time. The multiple clock oscillator circuits and the multiplexer(s) are fabricated as an integrated circuit to minimize the degrading effects of weather and dust, to provide a fixed capacitive value and inverter bandwidth product, and to improve clock generator stability.

Abstract translation: 高频时钟发生器具有能够提供耦合到多个振荡器电路的各种输出频率的多个石英晶体。 来自每个振荡器电路的输出线耦合到一个或多个复用器，使得用户可以同时选择一个或多个输出频率。 多个时钟振荡器电路和多路复用器被制造为集成电路，以最小化天气和灰尘的劣化影响，提供固定的电容值和逆变器带宽乘积，并改善时钟发生器的稳定性。

公开(公告)号：US3902140A

公开(公告)日：1975-08-26

申请号：US29846672

申请日：1972-10-18

Applicant: GREBENE ALAN B

Inventor： GREBENE ALAN B

IPC: H03B1/00 ,  H03K3/282 ,  H03K4/02 ,  H03K4/06 ,  H03K4/52 ,  H03K7/06 ,  H04L27/12

CPC classification number: H03K4/06 ,  H03B2201/0275 ,  H03B2201/0283 ,  H03K3/2821 ,  H03K4/026 ,  H03K4/52 ,  H03K7/06 ,  H04L27/12

Abstract: A digitally controlled oscillator includes an emitter coupled multivibrator with weighted current sources driving the timing capacitor of the multivibrator the weighted current sources being driven by a binary input signal to produce an output frequency corresponding to the binary weight of the input signal. The multivibrator produces output waveforms of either square, triangular or sine waveshapes. The sine wave output is accomplished by the use of anti-parallel diodes in conjunction with the triangular wave output circuitry.

公开(公告)号：WO2013060854A2

公开(公告)日：2013-05-02

申请号：PCT/EP2012071276

申请日：2012-10-26

Applicant: INTEL MOBILE COMM GMBH ,  THALLER EDWIN ,  NONIS ROBERTO

Inventor： THALLER EDWIN ,  NONIS ROBERTO

CPC classification number: H03B5/124 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1265 ,  H03B2201/0208 ,  H03B2201/0283 ,  H03J2200/10

Abstract: One embodiment of the present invention relates to a digital controlled oscillator. The oscillator includes an oscillator circuit, a varactor array, and a control circuit. The oscillator circuit receives a control word and a signal and generates an oscillator clock signal from the signal at a frequency selected by the control word. The varactor array has a first array of varactor cells having incremental capacitance values and a second array of varactor cells having equal capacitance values. The split varactor array provides a capacitance value. A control circuit is coupled to the oscillator circuit and controls the split varactor array according to the control word. The control circuit sets varactor cells of the split varactor array on or off.

Abstract translation: 本发明的一个实施例涉及一种数字控制振荡器。 振荡器包括振荡器电路，变容二极管阵列和控制电路。 振荡器电路接收控制字和信号，并以由控制字选择的频率从信号产生振荡器时钟信号。 变容管阵列具有具有增量电容值的变容管单元的第一阵列和具有相等电容值的变容管单元的第二阵列。 分路变容二极管阵列提供电容值。 控制电路耦合到振荡器电路并且根据控制字控制分裂变容二极管阵列。 控制电路开启或关闭分离变容二极管阵列的变容二极管单元。

公开(公告)号：WO2005104347A1

公开(公告)日：2005-11-03

申请号：PCT/US2005/007045

申请日：2005-03-03

Applicant: QUALCOMM Incorporated ,  PELUSO, Vicenzo Filip Andre

Inventor： PELUSO, Vicenzo Filip Andre

IPC: H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1287 ,  H03B5/1293 ,  H03B2201/0266 ,  H03B2201/0283 ,  H03J1/005 ,  H03J2200/10

Abstract: A programmable capacitor bank includes multiple tuning elements (510y). Each tuning element includes two tuning capacitors (513y, 514y) and a pass transistor (516y) that electrically connects or disconnects the capacitors to/from common nodes. (V1z, Vrz, V1y, Vry) For a thermometer decoded capacitor bank, the tuning capacitors for all tuning elements have equal capacitance. (Ct) Each tuning element further includes at least one pull-up transistor (522y, 524y) that provides high bias voltage for the pass transistor and at least one pull-down transistor (526y, 528y) that provides low bias voltage for the pass transistor. The multiple tuning elements may be arranged in a ladder topology such that (1) the tuning elements are turned on in sequential order starting from one end of the ladder and going toward the other end of the ladder and (2) each tuning element receives biasing from a preceding tuning element and provides biasing to a succeeding tuning element. The capacitor bank may be used for VCOs and other circuits.

Abstract translation: 可编程电容器组包括多个调谐元件（510y）。 每个调谐元件包括两个调谐电容器（513y，514y）和将电容器与公共节点电连接或断开的传输晶体管（516y）。 （V1z，Vrz，V1y，Vry）对于温度计解码电容器组，用于所有调谐元件的调谐电容器具有相等的电容。 （Ct）每个调谐元件还包括为传递晶体管提供高偏置电压的至少一个上拉晶体管（522y，524y）和为通路提供低偏置电压的至少一个下拉晶体管（526y，528y） 晶体管。 多个调谐元件可以被布置成梯形拓扑结构，使得（1）调谐元件从梯子的一端开始并且朝着梯子的另一端顺序地接通，并且（2）每个调谐元件接收偏置 并且向后续的调谐元件提供偏置。 电容器组可用于VCO和其他电路。

公开(公告)号：WO2007050663A2

公开(公告)日：2007-05-03

申请号：PCT/US2006041585

申请日：2006-10-25

Applicant: MICROCHIP TECH INC ,  KUPPUSAMY VANITHA ,  ROGERS CLARK

Inventor： KUPPUSAMY VANITHA ,  ROGERS CLARK

IPC: H03B1/00

CPC classification number: H03M1/0872 ,  H03B2200/0034 ,  H03B2200/0048 ,  H03B2201/0283 ,  H03L1/00 ,  H03M1/742

Abstract: Current sources are selectively coupled to a current controlled frequency determining circuit of an oscillator. A buffer amplifier has an input coupled to the current controlled frequency determining circuit of the oscillator and the buffer amplifier output is selectively coupled to the current sources not coupled to the frequency determining circuit of the oscillator. The buffer amplifier output maintains substantially the voltage of the current controlled frequency determining circuit on each of the current sources not coupled to the frequency determining circuit so that when any current source is coupled thereto, there is substantially no voltage difference therebetween. This substantially prevents generation of undesirable frequency spikes during coupling of the current sources to the frequency determining circuit of the oscillator.

Abstract translation: 电流源选择性地耦合到振荡器的电流控制频率确定电路。 缓冲放大器具有耦合到振荡器的电流控制频率确定电路的输入，并且缓冲放大器输出选择性地耦合到未耦合到振荡器的频率确定电路的电流源。 缓冲放大器输出基本上维持不耦合到频率确定电路的每个电流源上的电流控制频率确定电路的电压，使得当任何电流源耦合到其上时，它们之间基本上没有电压差。 这实质上防止了在将电流源耦合到振荡器的频率确定电路期间产生不期望的频率尖峰。

公开(公告)号：WO0067325A8

公开(公告)日：2001-05-25

申请号：PCT/US0011801

申请日：2000-05-02

Applicant: SILICON WAVE INC

Inventor： MUCKE LARS HENRIK ,  HULL CHRISTOPHER D ,  JANSSON LARS G

IPC: H01L27/08 ,  H03B1/00 ,  H03B5/12

CPC classification number: H03F3/45085 ,  H01L27/0805 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/124 ,  H03B5/1265 ,  H03B2201/0266 ,  H03B2201/0283 ,  H03F1/56 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03J2200/10 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18

Abstract: A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or "binary" varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance of the binary capacitor can be changed from simply by changing the polarity of the applied D.C. voltage from a positive to a negative value. A plurality of binary capacitors are configured in a parallel arrangement to produce a digitally controlled capacitor. The digitally controlled capacitor can be used in any integrated circuit requiring a tightly controlled tuned network. One application is a voltage-controlled oscillator (VCO) wherein the center output frequency of the VCO is calibrated by digitally modifying the capacitance of the VCO's digitally controlled capacitor.

Abstract translation: 一种使用MOS-FET器件数字控制集成电路器件的电容的方法和装置。 根据本发明的一个方面，提出了一种一位或“二进制”变容二极管，其中MOS-FET器件的栅极 - 体积电容表现出对其栅极和阱注入区域之间施加的直流电压的依赖性。 可以简单地通过将所施加的直流电压的极性从正值改变为负值来改变二进制电容器的电容。 多个二进制电容器被配置成并联布置以产生数字控制的电容器。 数字控制电容器可用于需要严格控制的调谐网络的任何集成电路中。 一种应用是压控振荡器（VCO），其中VCO的中心输出频率通过数字修改VCO的数字控制电容器的电容来校准。

公开(公告)号：EP1481469B1

公开(公告)日：2008-11-12

申请号：EP03704288.4

申请日：2003-02-04

Applicant: Infineon Technologies AG

Inventor： OEHM, Jürgen

IPC: H03B1/04

CPC classification number: H03B5/1271 ,  H03B5/129 ,  H03B2201/0283

Abstract: Disclosed is a circuit system generating a reference current (Iref) and an oscillator circuit which comprises said circuit system and a capacitor (8) that is connected to the input of a voltage-controlled source of electric power (1). Said capacitor (8) is triggered by two inter-switchable amplifiers (4, 6) with different driving capacities (gm1, gm2). According to said principle, an LC oscillator (14), for example, can be electrically controlled while being fed with the reference current (Iref) at a particularly low noise level.

公开(公告)号：EP0078857B1

公开(公告)日：1986-04-30

申请号：EP81109520.7

申请日：1981-11-05

Applicant: Hewlett-Packard Company

Inventor： Kovalick, Al ,  Hassun, Rolly

IPC: H04L27/04 ,  H03C1/00 ,  H03B21/02

CPC classification number: H03C1/00 ,  H03B21/02 ,  H03B28/00 ,  H03B2201/0283 ,  H03C2200/0029 ,  H04L27/04