Abstract:
An amplifier having programmable operational characteristics and a serial communications interface are fabricated on an integrated circuit (IC). The serial communications interface controls the operational characteristics, e.g., gain, frequency response, etc., of the amplifier. A multiplexer (MUX) may also be included on the IC and may be controlled by the serial communications interface. Status of the amplifier may also be obtained through the serial communications interface. The pin count of the IC package may be kept to a minimum by using the serial communications interface.
Abstract:
The present invention provides a switchable gain amplifier comprising a high-pass filter pole. The switchable gain amplifier comprises first and second input nodes for receiving first and second components of a differential input signal. A first input terminal of a first differential amplifier is coupled to the first input node, and a first input terminal of a second differential amplifier is coupled to the second input node. A first variable resistance is coupled between the first input terminal of the first differential amplifier and a second input terminal of the first differential amplifier. A second variable resistance is coupled between the first input terminal of the second differential amplifier and a second input terminal of the second differential amplifier. A differential capacitor is coupled between the second input terminal of the first differential amplifier and the second input terminal of the second differential amplifier.
Abstract:
At least two innovations are used to overcome the limitations of conventional transimpedance or high impedance optical receiver front end amplifiers. The innovations are a) multiple stage equalization of a high-feedback resistor, low-gain transimpedance amplifier to obtain high sensitivity, and b) range switching of feedback resistors and equalization capacitors to obtain high overload. With these approaches, it is possible to design an optical receiver operating at the intrinsic limits of available device technology.
Abstract:
La présente invention concerne un dispositif amplificateur de charges à gain de conversion élevé qui comprend un amplificateur en tension et une boucle de rétroaction entre la sortie et l'entrée de l'amplificateur, tel que la boucle de rétroaction est constituée d'une capacité connectée en série avec un diviseur de tension, le diviseur de tension comprenant au moins une capacité variable connectée entre un point intermédiaire de tension et une tension de polarisation variable et étant agencé pour que la tension au point intermédiaire soit inférieure à la tension de sortie de l'amplificateur.
Abstract:
An amplifier assembly (100) includes an amplifier (102) having an input terminal, an output terminal and a feedback terminal; a first feedback path connecting the output terminal to the feedback terminal; a second feedback path connecting the output terminal to the feedback terminal; a switch (124) positioned in the second feedback path, the switch (124) opening or closing in response to a voltage at the output terminal relative to a breakpoint, when the switch (124) is open, the amplifier assembly (100) has a first gain and when the switch (124) is closed, the amplifier assembly (100) has a second gain; and a thermally variable element (152) connected to the switch (124), the thermally variable element (152) configured to generate a compensation voltage to maintain the breakpoint in response to varying temperature of the switch (152).
Abstract:
A gain switching circuit (3) that switches a conversion gain of a preamp (2) , which outputs a voltage signal upon amplifying an output current of a photo-detecting element (1) that converts a burst-form optical signal into an electrical signal and with which a series circuit, formed with a first resistor (6) and a first switching element (9) , and a series circuit, formed with a second resistor (7) and a second switching element (10) are connected in parallel to a feedback resistor (2B). The switching circuit further includes a gate signal generating circuit that generates, upon receiving an output of the pre-amplifier, a gate signal for a first and second operating unit.
Abstract:
1. 청구범위에 기재된 발명이 속한 기술분야 본 발명은, 본 발명은 초광대역 전송 시스템의 수신신호 전력 제어 방법과 상기 방법을 실현시키기 위한 프로그램을 기록한 컴퓨터로 읽을 수 있는 기록매체에 관한 것임. 2. 발명이 해결하려고 하는 기술적 과제 본 발명은, 본 발명은 상기한 바와 같은 문제점을 해결하기 위하여 제안된 것으로, 서로 다른 주파수 대역을 사용함으로써 생기는 수신신호의 전력차를 수신부에 있는 VGA 앞단에서 미리 처리함으로써, VGA의 역할을 간소화하여 초기 수렴속도를 빠르게 하기 위한 초광대역 전송 시스템의 수신신호 전력 제어 방법을 제공하는데 그 목적이 있음. 3. 발명의 해결방법의 요지 본 발명은, 다중 주파수 대역을 사용하는 전송 시스템에서 전압 이득 증폭기(VGA) 앞단에 배치된 전-이득 제어부(PGC)를 구비하여, 상기 PGC가 수신되는 신호의 주파수 대역에 따른 전력의 차이를 보상하기 위한 초광대역 전송 시스템의 수신신호 전력 제어 방법에 있어서, 상기 전송 시스템의 송신부에서 사용한 다중 주파수 대역을 감지하는 제 1단계; 다중 주파수 대역 사용에 따른 수신신호 세기의 차이의 전력 이득값을 결정하는 제 2단계; 및 상기 수신신호 세기의 차이의 전력 이득값에 따라 수신신호 전력의 보상을 수행하는 제 3단계를 포함함. 4. 발명의 중요한 용도 본 발명은 초광대역(UWB) 전송 시스템에 이용됨.
Abstract:
A method for controlling a receiving signal power of a ultra wide band transmission system is provided to mount a PGC in a front end of a VGA, and to compensate a power difference in accordance with frequency bands of received signals by the PGC, thereby providing a faster initial convergence by simplifying a VGA operation. In a ultra wide band transmission system, a receiving unit is comprised of an antenna(600), a pre-select filter(610), an LNA(Low Noise Amplifier)(620), modulators(630,631), LPFs(Low Pass Filter)(640,641), VGAs(660,661), ADCs(Analog/Digital Converters)(670,671), a timing recovery/demodulator(680), and PGCs(650,651). The modulators(630,631) detect frequency bands used by a transmission unit in the ultra wide band transmission system. The PGCs(650,651) decide a power gain value of an intensity difference of receiving signals according to multi frequency bands, and compensate the power gain value.