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    EYE PATTERN TRIGGERING BASED ON SYMBOL TRANSITION
    21.
    发明申请
    EYE PATTERN TRIGGERING BASED ON SYMBOL TRANSITION 审中-公开
    基于符号转换的眼睛图案触发

    公开(公告)号：WO2015054297A1

    公开(公告)日：2015-04-16

    申请号：PCT/US2014/059548

    申请日：2014-10-07

    Applicant: QUALCOMM INCORPORATED

    Inventor： WILEY, George Alan ,  LEE, Chulkyu

    IPC: H04L1/24 ,  H04L1/20

    CPC classification number: H04L7/042 ,  H04L1/205 ,  H04L1/206 ,  H04L1/247 ,  H04L5/20 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0294 ,  H04L25/0298 ,  H04L25/4917

    Abstract: System, methods and apparatus are described that facilitate tests and measurements related to multi-wire, multi-phase communications links. Information is transmitted in N-phase polarity encoded symbols and an eye pattern corresponding to the symbols is generated such that the symbols are aligned with a trigger for each symbol that corresponds to a clock edge used to sample the symbols. The eye pattern may be used to determine sufficiency of setup times in the communication links and other such characteristics defining a communications channel capabilities.

    Abstract translation: 描述了便于与多线，多相通信链路相关的测试和测量的系统，方法和装置。 信息以N相极性编码的符号发送，并且生成与符号相对应的眼图，使得符号与对应于用于采样符号的时钟边缘的每个符号的触发对齐。 眼图可以用于确定通信链路中的建立时间的充分性以及定义通信信道能力的其它这样的特性。

    METHOD AND APPARATUS FOR PROCESSING A MULTI-LEVEL FSK SIGNAL
    22.
    发明申请
    METHOD AND APPARATUS FOR PROCESSING A MULTI-LEVEL FSK SIGNAL 审中-公开
    用于处理多级FSK信号的方法和装置

    公开(公告)号：WO98036545A1

    公开(公告)日：1998-08-20

    申请号：PCT/US1998/001029

    申请日：1998-01-20

    IPC: H04L1/24 ,  H04L25/02 ,  H04L27/152 ,  H04L27/14

    CPC classification number: H04L25/0262 ,  H04L1/247 ,  H04L27/1525

    Abstract: A receiver (100) is used for processing a multi-level FSK signal, comprising a converter (101) for converting the multi-level FSK signal into a sequence of state transitions, and a baud rate detector (111). The baud rate detector (111) comprises in a plurality of sampling intervals, wherein each of the plurality of sampling intervals is offset by a first predetermined time from other sampling intervals, and wherein each of the plurality of sampling intervals is further subdivided into a plurality of recording intervals, a plurality of counters (502-508) for counting the sequence of state transitions that occur during at least a minimum number of the plurality of recording intervals. The baud rate detector (111) further comprises a baud rate detection circuit (524) for detecting the desired baud rate based on counts recorded in a memory (522).

    Abstract translation: 接收器（100）用于处理多级FSK信号，包括用于将多级FSK信号转换成状态转换序列的转换器（101）和波特率检测器（111）。 波特率检测器（111）包括多个采样间隔，其中多个采样间隔中的每一个从其他采样间隔偏移第一预定时间，并且其中多个采样间隔中的每一个被进一步细分为多个 多个计数器（502-508），用于计数在所述多个记录间隔的至少最小数目期间发生的状态转换序列。 波特率检测器（111）还包括用于基于记录在存储器（522）中的计数来检测所需波特率的波特率检测电路（524）。

    SYMBOL DETECTION AND ERROR CORRECTION CODING IN A LOCAL AREA NETWORK
    23.
    发明申请
    SYMBOL DETECTION AND ERROR CORRECTION CODING IN A LOCAL AREA NETWORK 审中-公开
    本地区网络中的符号检测和错误校正编码

    公开(公告)号：WO1990004295A1

    公开(公告)日：1990-04-19

    申请号：PCT/US1989004503

    申请日：1989-10-12

    Applicant: CONCORD COMMUNICATIONS, INC.

    Inventor： CONCORD COMMUNICATIONS, INC. ,  FURLONG, Darrell

    IPC: H04L01/24

    CPC classification number: H04L25/06 ,  H04L1/247

    Abstract: A symbol detection and correction scheme for local area network modems, especially those which receive one of three symbols at any given time, such as those operating in accordance with the IEEE 802.4 standard. The invention significantly improves the bit error rate observed by the layer above the modem. The modem operates on a received signal with a pair of slicers. One slicer operating as a two-symbol decoder, and a second slicer operates as a three-symbol decoder. A receiver state machine is used to keep track of which portion of a frame is currently expected to be received. Depending upon the particular context, one or both of the slicer outputs are used by the state machine to determine which of the three symbols was received. For example, when the receiver is in a state where only one of two data symbols are expected, and no control symbols are expected, only the two-symbol slicer output is used. The three-symbol slicer output, and logical combinations of the three-symbol slicer output and the two-symbol slicer output, are used at other times. The receiver state machine recognizes errors in pseudo-silence, start delimiter, and end-delimiter sequences without reporting such errors to the upper level, thereby greatly decreasing the error rate observed there.

    Pulse trio detecting circuit
    24.
    发明专利
    Pulse trio detecting circuit 失效
    脉冲三极管检测电路

    公开(公告)号：JPS5954358A

    公开(公告)日：1984-03-29

    申请号：JP16400782

    申请日：1982-09-22

    Applicant: Fujitsu Ltd

    Inventor： KUTSUWADA NORIYUKI ,  KAJIWARA SHINJI ,  MOTOI HIDESUKE

    IPC: H04L25/02 ,  H04L1/24

    CPC classification number: H04L1/247

    Abstract: PURPOSE:To form a digitized pulse trio detecting circuit, by detecting a three consecutive pulse at the 1st gate circuit and detecting a bipolar violation generated only at the first or last pulse at the 2nd gate circuit. CONSTITUTION:A pulse trio signal is inputted to an input terminal from a bipolar/unipolar converting circuit 10, the three consecutive pulse is outputted to the output of an OR gate 11, and it is transferred sequentially to each stage of a shift register 12. Further, a violation detecting circuit 13 detects the bipolar violation at the 1st pulse position and gives the result of detection to a shift register 15. Since each bit of the shift registers 12 and 15 is ''111'', ''1'' is outputted from both AND gates 16, 18, and then ''1'' is outputted from an AND gate 17 and it is detected at a counter 14.

    Abstract translation: 目的：通过在第一门电路检测三个连续的脉冲并检测仅在第二门电路的第一个或最后一个脉冲产生的双极违例，形成一个数字脉冲三重检测电路。 构成：从双极/单极转换电路10向输入端子输入脉冲三重信号，将三个连续的脉冲输出到或门11的输出，并将其顺序地传送到移位寄存器12的各个级。 此外，违规检测电路13检测在第一脉冲位置处的双极性违规，并将检测结果给予移位寄存器15.由于移位寄存器12和15的每个位为“111”，“1” 从AND门16,18输出，然后从AND门17输出“1”，并在计数器14检测。

    Code error detecting circuit
    25.
    发明专利
    Code error detecting circuit 失效
    代码错误检测电路

    公开(公告)号：JPS5744351A

    公开(公告)日：1982-03-12

    申请号：JP11840380

    申请日：1980-08-29

    Applicant: Fujitsu Ltd

    Inventor： HIDA NORIYUKI ,  FUJIMOTO NAONOBU

    IPC: H03M5/16 ,  H03M13/00 ,  H04L1/24 ,  H04L25/49

    CPC classification number: H04L1/247

    Abstract: PURPOSE:To simplify the circuit constitution of a code error detecting circuit for HDBn codes, by monitoring digital integral values of the HDBn codes by using a universal shift register. CONSTITUTION:The principal part of an error detecting circuit which detects errors of HDBn (High Density Bipolar n) codes used by a digital transmission system consists of two stages of universal shift registers and two AND gates 22 and 24. The universal shift registers 20 are capable of transferring data to left and right and this operation is utilized to monitor digital integral values of HDBn codes. An HDBn code free from a code error never has >=3 successive pulses of the same polarity, so the largest digital integral value of the HDBn is 2 and when the digital integral value exceeds two, the code is regarded as an error.

    Abstract translation: 目的：为了简化HDBn码的码错误检测电路的电路结构，通过使用通用移位寄存器监视HDBn码的数字积分值。 构成：检测由数字传输系统使用的HDBn（高密度双极性n）码的误差的误差检测电路的主要部分由两级通用移位寄存器和两个与门22和24组成。通用移位寄存器20为 能够将数据传输到左和右，并且该操作被用于监视HDBn码的数字积分值。 没有代码错误的HDBn代码从不具有相同极性的> = 3个连续脉冲，因此HDBn的最大数字积分值为2，当数字积分值超过2时，该代码被认为是错误。

    Code detecting circuit
    27.
    发明专利
    Code detecting circuit 失效
    代码检测电路

    公开(公告)号：JPS59122157A

    公开(公告)日：1984-07-14

    申请号：JP22872482

    申请日：1982-12-28

    Applicant: Fujitsu Ltd

    Inventor： MOTOI HIDESUKE ,  KUTSUWADA NORIYUKI ,  KAJIWARA SHINJI

    IPC: H03M5/14 ,  H04L1/24 ,  H04L25/02 ,  H04L25/49

    CPC classification number: H04L1/247

    Abstract: PURPOSE:To simplify the PCM transmitter and to reduce cost by providing a pulse trio detecting section to a BnZs/NRZ code detecting circuit. CONSTITUTION:A pulse trio inputted to a terminal 15 is applied to a shift register 19 as an NRZ signal. When contents of the shift register 19 are (1,1,1,0) that is, a pulse trio is detected, a detecting circuit 24 brings the level of a signal (e) to (1). When contents of the shift register are (0,0,1,0) that is, the pattern of a bipolar violation is checked, a detecting circuit 25 brings the level of a signal (f) to (1). When both signals (e), (f) are (1), a changeover switch 8 is driven, an incoming line 3 and an outgoing line 4 are connected in a loop so as to attain the system test of the PCM repeater system.

    Abstract translation: 目的：为了简化PCM发送器，并通过向BnZ / NRZ码检测电路提供脉冲三重检测部分来降低成本。 构成：输入到端子15的脉冲三重态作为NRZ信号施加到移位寄存器19。 当移位寄存器19的内容是（1,1,1,0）即检测到脉冲三重时，检测电路24将信号（e）的电平变为（1）。 当移位寄存器的内容为（0,0,1,0）即是双极违规的模式时，检测电路25将信号（f）的电平变为（1）。 当信号（e），（f）都为（1）时，转换开关8被驱动，输入线3和出线4以循环方式连接，以便实现PCM中继器系统的系统测试。

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