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公开(公告)号：US12021300B2
公开(公告)日：2024-06-25
申请号：US17617584
申请日：2019-12-19
Applicant: HuiZhou TCL Mobile Communication Co., Ltd.
Inventor： Wei Chen , Zhiwei Chen , Pan Zhang
CPC classification number: H01Q1/38 , H01Q1/243 , H01Q1/48 , H01Q1/50 , H01Q5/335 , H01Q5/50 , H04M1/0277 , H04M2201/06
Abstract: Disclosed is a mobile terminal. The mobile terminal comprises a body, an insulating bezel surrounding the periphery of the body, and a wire that is located in the insulating bezel and that acts as an antenna. The wire comprises a first line segment and at least two bending line segments that are connected to the first line segment. The bending line segments bend and extend into convex shapes from the connecting position of the first line segment, at least one bending line segment acts as the ground point of the antenna, and at least one bending line segment acts as the feed point of the antenna.
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公开(公告)号：US09768319B2
公开(公告)日：2017-09-19
申请号：US15159182
申请日：2016-05-19
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Koichiro Kamata
IPC: H01L29/78 , H01L29/786 , H03C1/36 , G06K19/077 , H01L23/66 , H01L27/06 , H01L49/02
CPC classification number: H01L29/7869 , G06K19/07775 , H01L23/66 , H01L27/0629 , H01L28/20 , H01L28/40 , H01L29/78693 , H01L29/78696 , H01L2223/6677 , H03C1/36 , H04M2201/04 , H04M2201/06
Abstract: A modulation circuit includes a load and a transistor serving as a switch. The transistor has an oxide semiconductor layer in which hydrogen concentration is 5×1019/cm3 or less. The off-state current of the transistor is 1×10−13 A or less. A modulation circuit includes a load, a transistor serving as a switch, and a diode. The load, the transistor, and the diode are connected in series between the terminals of an antenna. The transistor has an oxide semiconductor layer in which hydrogen concentration is 5×1019/cm3 or less. An off-state current of the transistor is 1×10−13 A or less. On/off of the transistor is controlled in accordance with a signal inputted to a gate of the transistor. The load is a resistor, a capacitor, or a combination of a resistor and a capacitor.
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23.发明授权Methods and apparatus for improving device functionality during long blocking UICC operations 有权在长时间阻止UICC操作期间改进设备功能的方法和设备公开(公告)号：US09325835B2
公开(公告)日：2016-04-26
申请号：US14293946
申请日：2014-06-02
Applicant: QUALCOMM Incorporated
Inventor： Jiang Zhang , Michele Berionne , Aram Perez
CPC classification number: H04M1/72569 , G06K19/07739 , H04L41/5038 , H04L43/00 , H04L43/16 , H04L43/50 , H04L69/02 , H04M2201/06 , H04W68/00
Abstract: Methods and apparatuses are presented herein for improved operation of a Universal Integrated Circuit Card (UICC) of one or more user equipment (UE). For example, an example method of wireless communications is presented, which may include monitoring, by a UE, one or more items received from a UICC of the UE during a UICC operation. In addition, the example method may also include determining that at least one of (a) a number of the one or more items having a first item type exceeds a threshold number, or (b) an elapsed time since the UICC operation started exceeds a threshold time. Moreover, the example method may include providing, based on the determining, a notification to a user interface associated with the UE indicating that the UICC operation is ongoing.
Abstract translation: 本文中给出了用于改进一个或多个用户设备（UE）的通用集成电路卡（UICC）的操作的方法和装置。 例如，呈现无线通信的示例方法，其可以包括由UE监视在UICC操作期间从UE的UICC接收的一个或多个项目。 此外，示例性方法还可以包括确定（a）具有第一项目类型的一个或多个项目的数量中的至少一个超过阈值数，或（b）自UICC操作开始以来的经过时间超过 阈值时间 此外，示例性方法可以包括：基于确定向与UE指示的用户界面的通知，指示UICC操作正在进行。
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24.发明授权1-chip microcomputer having controlled access to a memory and IC card using the 1-chip microcomputer 有权使用1片微型计算机控制对存储器和IC卡的访问的1片微型计算机公开(公告)号：US07213117B2
公开(公告)日：2007-05-01
申请号：US09805199
申请日：2001-03-14
Applicant: Masaki Wakabayashi , Ryuichi Ogawa , Kazuhiro Yaegawa , Susumu Kurioka , Kenji Ohno , Tadao Takeda , Hiroki Sutou , Masahiro Yoshizawa
Inventor： Masaki Wakabayashi , Ryuichi Ogawa , Kazuhiro Yaegawa , Susumu Kurioka , Kenji Ohno , Tadao Takeda , Hiroki Sutou , Masahiro Yoshizawa
IPC: G06F12/14
CPC classification number: H04Q3/64 , H04M3/51 , H04M2201/06 , H04M2201/34 , H04M2201/36 , H04M2201/38 , H04Q11/0471 , H04Q2213/13003 , H04Q2213/1305 , H04Q2213/1307 , H04Q2213/13072 , H04Q2213/13095 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13209 , H04Q2213/13305 , H04Q2213/1332 , H04Q2213/13322
Abstract: A 1-chip microcomputer of the present invention has (a) a monitor flag for setting a flag indicating that a specified address space is accessed, (b) an access permission address range setting register, for setting an address range in which an access is permitted while the flag is set, (c) an access permission area detection circuit for judging whether the access is made within the address range thus set, (d) an access permission setting register, for setting whether or not an access with respect to an address other than the address range should be permitted, and (e) memory read-out control circuit and memory writing control circuit for controlling an access with respect to a nonvolatile memory based on a result thus judged and content set by the access permission setting register. With the arrangement, it is possible to provide a 1-chip microcomputer that maintains the security among application programs.
Abstract translation: 本发明的1片微型计算机具有（a）用于设定表示指定的地址空间被访问的标志的监视标志，（b）访问许可地址范围设定寄存器，用于设定访问权限的地址范围 （c）用于判断在如此设置的地址范围内是否进行访问的访问允许区域检测电路，（d）访问许可设置寄存器，用于设置是否访问相对于 应允许地址范围以外的地址，以及（e）存储器读出控制电路和存储器写入控制电路，用于基于由此判断的结果来控制对非易失性存储器的访问，以及由访问许可设置寄存器设置的内容 。 通过这种布置，可以提供一种在应用程序之间保持安全性的1片微型计算机。
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公开(公告)号：US20030071317A1
公开(公告)日：2003-04-17
申请号：US10101162
申请日：2002-03-20
Inventor： Takasumi Ohyanagi , Atsuo Watanabe
IPC: H01L029/76
CPC classification number: H01L29/66681 , G09G3/28 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/1083 , H01L29/66265 , H01L29/66674 , H01L29/7317 , H01L29/7824 , H04M3/005 , H04M3/18 , H04M2201/06
Abstract: An N-channel MOS field-effect transistor on an SOI substrate including a source electrode, drain and gate electrodes both disposed via a field oxide film, a gate oxide film, a high concentration P-type layer, a high concentration N-type layer contacting the source electrode and the gate oxide film, a high concentration N-type layer contacting the drain electrode, a p-body layer contacting the high concentration P-type and N-type layers and the gate oxide film. In this transistor, an N-type layer with a concentration higher than that of a drain region contacting the p-body layer constitutes a region covering at most 95% of the source-drain distance. Further, an N-type region having a concentration from 3null1016/cm3 to 1null1022/cm3 is provided near a buried oxide film under the drain electrode.
Abstract translation: 在SOI衬底上的N沟道MOS场效应晶体管，其包括经由场氧化膜设置的源电极，漏极和栅电极，栅极氧化膜，高浓度P型层，高浓度N型层 与源电极和栅极氧化膜接触，接触漏电极的高浓度N型层，与高浓度P型和N型层接触的p体层和栅氧化膜。 在该晶体管中，具有高于与p体层接触的漏极区域的浓度的N型层构成覆盖源极 - 漏极距离的至多95％的区域。 此外，在漏电极下方的埋置氧化膜附近设置浓度为3×10 16 / cm 3至1×10 22 / cm 3的N型区域。
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Patent Agency Ranking
公开(公告)号：JP2004524682A
公开(公告)日：2004-08-12
申请号：JP2002561285
申请日：2002-01-25
Applicant: インフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG
Inventor： エメリクス、アンデルス , シェーディン、ホカン , ヘルベルク、ヘンリク
IPC: H01L27/04 , H01L21/822 , H04M3/00
CPC classification number: H04M3/005 , H04M2201/06
Abstract: 可変出力電圧を出力するように設計された回路において、半導体素子の基板は、レギュレータに接続され、特に、回路基板の電位よりも低い電位に接続されるスイッチに接続される。 回路は、例えば、加入者回線インターフェイス回路（ＳＬＩＣ）に用い得る。
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公开(公告)号：JP6090890B2
公开(公告)日：2017-03-08
申请号：JP2016517081
申请日：2014-06-03
Applicant: クアルコム,インコーポレイテッド
Inventor： ジアン・ジャン , ミッシェル・ベリオン , アラム・ペレス
CPC classification number: H04M1/72569 , G06K19/07739 , H04L41/5038 , H04L43/00 , H04L43/16 , H04L43/50 , H04L69/02 , H04W68/00 , H04M2201/06
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公开(公告)号：JP3783156B2
公开(公告)日：2006-06-07
申请号：JP2001318969
申请日：2001-10-17
Applicant: 株式会社日立製作所
IPC: H01L29/786 , H01L21/331 , H01L21/336 , H01L21/762 , H01L21/77 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L21/84 , H01L27/06 , H01L27/08 , H01L27/12 , H01L29/08 , H01L29/10 , H01L29/73 , H01L29/78 , H04M3/00 , H04M3/18
CPC classification number: H01L29/66681 , G09G3/28 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/1083 , H01L29/66265 , H01L29/66674 , H01L29/7317 , H01L29/7824 , H04M3/005 , H04M3/18 , H04M2201/06
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公开(公告)号：US20240310887A1
公开(公告)日：2024-09-19
申请号：US18121508
申请日：2023-03-14
Applicant: QUALCOMM Incorporated
Inventor： Xingyi HUA , David Zixiang YANG , Francesco GATTA
CPC classification number: G06F1/26 , H04M1/725 , H04M2201/02 , H04M2201/04 , H04M2201/06 , H04M2201/14
Abstract: A dual-VIO integrated circuit is configurable into either a first configuration in which a VIO power supply voltage has a first value or into a second configuration in which the VIO power supply voltage has a second value. The dual-VIO integrated circuit includes a smart start-up detection circuit that detects whether the integrated circuit is in the first configuration or the second configuration.
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公开(公告)号：US11856122B2
公开(公告)日：2023-12-26
申请号：US17608160
申请日：2020-05-09
Applicant: Honor Device Co., Ltd.
Inventor： Guotong Zhou , Dong Ma , Xinwen Xu , Yan Wang
CPC classification number: H04M1/236 , G06V40/1329 , H04M1/0277 , H04M2201/06
Abstract: An electronic device is provided. A lateral fingerprint recognition apparatus is in contact with a function button. An accommodating structure is arranged in the lateral fingerprint recognition apparatus. A stopping assembly is arranged on a side of a fingerprint hole close to the function button. Inserting a partial area of the stopping assembly into the accommodating structure enables the lateral fingerprint recognition apparatus, when pressed, to move in movement space of the accommodating structure on the side of the fingerprint hole close to the function button, so as to limit a displacement amount of the lateral fingerprint recognition apparatus within a specific range, implementing the functions of the lateral fingerprint recognition apparatus and of the function button, and preventing the lateral fingerprint recognition apparatus from being displaced from the originally designed position.
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