公开(公告)号：JPS515527B1

公开(公告)日：1976-02-20

申请号：JP7596969

申请日：1969-09-22

IPC: G06F11/10 ,  H03M13/00 ,  H04B1/00 ,  H04L1/10

公开(公告)号：JPS511107B1

公开(公告)日：1976-01-13

申请号：JP1856770

申请日：1970-03-02

IPC: H03M13/51 ,  G06F11/10 ,  G06K1/00 ,  G11B5/09 ,  G06F5/02 ,  G06F13/04 ,  H04L1/10

公开(公告)号：JPS5034363B1

公开(公告)日：1975-11-07

申请号：JP7482768

申请日：1968-10-14

IPC: G06F11/10 ,  B04B1/06 ,  G06F11/08 ,  H03M13/00 ,  H04L1/10

公开(公告)号：JPS5021202B1

公开(公告)日：1975-07-21

申请号：JP7494069

申请日：1969-09-20

IPC: H04L27/32 ,  H04L1/00 ,  H04L27/10 ,  H04L27/18 ,  H04L1/10

公开(公告)号：JPS5013462Y1

公开(公告)日：1975-04-24

申请号：JP9044570

申请日：1970-09-11

IPC: H04L1/00 ,  G06F11/00 ,  G06F11/14 ,  H04L13/00 ,  H04L29/02 ,  H04Q9/00 ,  H04Q9/14 ,  G06F15/46 ,  H04L1/10

公开(公告)号：JPS5013461Y1

公开(公告)日：1975-04-24

申请号：JP1416370

申请日：1970-02-12

IPC: G06F11/10 ,  H03M13/00 ,  H04L1/10

公开(公告)号：JPS508604B1

公开(公告)日：1975-04-05

申请号：JP3681870

申请日：1970-05-01

IPC: H04L1/00 ,  H04L1/12 ,  H04L1/16 ,  H04L1/10

公开(公告)号：JPS4935124Y1

公开(公告)日：1974-09-25

申请号：JP8999973

申请日：1973-07-31

IPC: H03M13/00 ,  H04L13/10 ,  H04L25/42 ,  H04L1/10

公开(公告)号：JPS59221811A

公开(公告)日：1984-12-13

申请号：JP9548683

申请日：1983-05-30

Applicant: NIPPON DENKI HOME ELECTRONICS

Inventor： ITOI TETSUSHI

IPC: H03M13/00 ,  G11B20/18 ,  G11B5/09 ,  H04L1/10

Abstract: PURPOSE:To manufacture a titled decoder by a simple circuit, to cause no block shift nor error detection leakage, and to execute exactly the operation by executing various signal processigs by the decoder, before information recorded in a recording medium is sent to a D/A converter. CONSTITUTION:A decoder has an RAM 4 for storing data of at least one field in order of an arriving block, and an RAM 7 for storing an error flag for showing a result of an error inspection (CRC check) of each block by ''1'' (error) and ''0'' (correct). Also, the decoder has an address generating part 11 for supplying simultaneously a common address to the respective address buses of the two RAMs, and a clock generating part 2 for generating and sending a time signal for executing a prescribed operation at a suitable time, to the data RAM 4, the flag RAM 7 and the address generating part 11. In this way, the decoder can be converted to an IC easily, can be made small-sized, no block shift nor error detection leakage is caused, and the operation is executed exactly.

公开(公告)号：JPS5915143U

公开(公告)日：1984-01-30

申请号：JP11037082

申请日：1982-07-21

IPC: G06F11/10 ,  G05B23/02 ,  G06F12/16 ,  G06F13/00 ,  G06F17/40 ,  G11C29/00 ,  H03M13/00 ,  G06F3/04 ,  H04L1/10