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公开(公告)号：WO01074000A1
公开(公告)日：2001-10-04
申请号：PCT/US2001/010444
申请日：2001-03-29
IPC: H03F1/02 , H03F3/193 , H04B1/10 , H04L1/10 , H01L27/06 , H03K5/01 , H03K6/04 , H04L25/08 , H04L27/08 , H04L27/14 , H04L27/22
CPC classification number: H04B1/109 , H03F1/0272 , H03F3/1935 , H03F2200/294 , H03F2200/372 , H03F2203/7239
Abstract: A radio frequency receiver (700) includes a first amplifier (701) that amplifies a radio frequency signal (720) into a first stage signal (721), a detector (707) that produces a bypass signal (731) when the signal strength of the received signal is sufficiently strong, and a switch (702) that provides the first stage signal (721) when the bypass signal (731) is asserted and the first stage signal (721) filtered by a radio frequency filter (703) and amplified by a second amplifier (704) when the bypass signal (731) is not asserted. The detector (707) also produces a bias control signal (727) and bias generators (709, 710) set the bias levels that increases as the signal level increases. The invention can be used to increase the range of linearity, and to reduce power consumption by reducing the amplification.
Abstract translation: RF接收器（700）包括将RF信号（720）放大为第一电平信号（721）的第一放大器（701），当第一放大器（701）输出第一电平信号时产生旁路信号（731）的检测器（707） 接收信号足够强，以及当旁路信号（731）通电时供应第一电平信号（721）的开关（702），该第一电平信号（721）由RF滤波器（703）滤波， 并且当旁路信号（731）未通电时由第二放大器（704）放大。 检测器（707）还产生偏振控制信号（727），而偏振发生器（709,710）设置随着信号电平增加而增加的偏振水平。 本发明通过减小放大率可以增加线性范围并降低功耗。
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2.发明申请METHOD AND APPARATUS FOR IMPLEMENTING WAVELET FILTERS IN A DIGITAL SYSTEM 审中-公开用于在数字系统中实现小波滤波器的方法和设备
公开(公告)号：WO00039952A1
公开(公告)日：2000-07-06
申请号：PCT/US1999/030547
申请日：1999-12-20
CPC classification number: H03H17/0266 , G06F17/148 , H03H2222/06
Abstract: A digital data system (100) provides 1-D, 2-D and 3-D capability and multi-band channel capability. Improved filter banks are created by generating a filter bank having an analysis portion and synthesis portion and obtaining wavelet coefficients (302) for each portion. The wavelet coefficients are expressed in a format capable of canonical signed digit (CSD) representation, such as integers (304). The canonical signed digit (CSD) representation is controlled by a value, N, selected to control resolution of the CSD coding. Optimized CSD-coded wavelet coefficients are used as filters for data signals (316).
Abstract translation: 本发明涉及具有一维，二维和三维容量以及全波道能力的数字数据系统（100）。 通过用分析部分和合成部分生成滤波器组并获得这些部分中的每一个的小波系数（302）来创建增强滤波器组。 小波系数以允许以数字形式（例如整数（304））的信号的标准表示的格式表示。 该表示由选定的值N控制，以根据此格式控制编码的分辨率。 如此编码和优化的小波系数使得可以过滤数据信号（316）。
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公开(公告)号：KR830002525B1
公开(公告)日：1983-11-07
申请号：KR800004018
申请日：1980-10-17
Applicant: SONY CORP
Inventor： TANAKA MASHATO , LWAMOTO IKUO , HURUKAWA SYUNSUKE , TOI TOSHITATA
IPC: H04L1/10
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公开(公告)号：JPS59219047A
公开(公告)日：1984-12-10
申请号：JP9287383
申请日：1983-05-26
Applicant: MITSUBISHI ELECTRIC CORP
Inventor： INAGI MAKOTO
Abstract: PURPOSE:To reduce the number of addresses by obtaining AND between an output of an ROM and input information by means of n-set of AND gates. CONSTITUTION:A row address signal (k) and a column address signal (i) are inputted to a memory 12 and output information aki . This information aki is inputted to n-set of AND gates 13 where the AND with information Xik inputted from an input terminal 11 is obtained. Information aki .Xik obtained at an output of the AND gates 13 is multiplied and added at a part comprising n-set of exclusive OR gates 14 and a D flip-flop 15 and its result is fetched to the D flip- flop 15 in the timing of a clock signal T1'. When mn-set of information V11- Xmn are inputted, one code is produced at first and fetched and outputted by a clock signal T2' generated immediately after the Xmn is inputted.
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Patent Agency Ranking
公开(公告)号：JPS56156043A
公开(公告)日：1981-12-02
申请号：JP5913380
申请日：1980-05-02
Applicant: NIPPON ELECTRIC CO
Inventor： KANETANI MASAHIKO
Abstract: PURPOSE:To prevent a mulfanction due to a pseudo flag pattern or a pseudo abort pattern, by adding a parity bit to a series data and then giving an alteration to the parity system with both the control data and the information data. CONSTITUTION:The clock A supplied from an oscillator OSC is divided into 9 parts by a 9-division circuit 2. The 9-divided clock B performs a parallel process through a parallel processing circuit 1, and the data c is counted by a 9-bit parity occurrence checking circuit 4 to perform a parity check. Then the parity P is inserted into the 9th bit at a parallel-series converting circuit 5 to be delivered in the form of a series data G. A switching between an odd parity and an even parity is carried out by the control pulses D and E which are delivered from an FF3.
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公开(公告)号：JPS5672553A
公开(公告)日：1981-06-16
申请号：JP14965479
申请日：1979-11-19
Applicant: NIPPON TELEGRAPH & TELEPHONE
Inventor： OOTANI KOUICHI
Abstract: PURPOSE:To detect a burst error continuously at a high speed and also by the real time, by generating a burst error signal by being set by an error pulse, and providing the FF which is reset when the number of continuous nonerror pulses has exceeded the prescribed value. CONSTITUTION:An error pulse which has been detected is provided to the set terminal S of the FF12 from the terminal 11, and the Q terminal is connected to the output terminal 13. As for the AND gate 16, when a output of the FF12 is in a high level, that is to say, a burst error signal is being generated, and also the error pulse is not provided from the AND gate 15, a clock pulse of the terminal 17, that is to say, a nonerror pulse is provided to the clock terminal CK of the counter 14 through the AND gate 16. Also, when the error pulse passes through the NAND gate 15, the counter 14 is reset. When the counter 14 has counted the prescribed value, its output is provided to the OR gate 19, and also it is provided to the reset terminal R of the FF12.
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