公开(公告)号：WO2010076189A1

公开(公告)日：2010-07-08

申请号：PCT/EP2009/067167

申请日：2009-12-15

Applicant: STMICROELECTRONICS S.R.L. ,  ALESSI, Enrico ,  RICCERI, Daniele

Inventor： ALESSI, Enrico ,  RICCERI, Daniele

IPC: C12Q1/68

CPC classification number: C12Q1/6837 ,  C12Q1/6844 ,  C12Q1/686 ,  C12Q2527/101 ,  C12Q2561/113 ,  C12Q2527/107

Abstract: A method for carrying out nucleic acid amplification, includes providing a reaction chamber (31), accommodating an array (36) of nucleic acid probes (37) at respective locations, for hybridizing to respective target nucleic acids; and introducing a solution (50) into the reaction chamber (31), wherein the solution (50) contains primers, capable of binding to target nucleic acids, nucleotides, nucleic acid extending enzymes and a sample including nucleic acids. The a structure of the nucleic acid probes (37) and of the primers so that a hybridization temperature (T H ) of the probes (37) is higher than an annealing temperature (T A ) of the primers, whereby hybridization and annealing take place in respective separate temperature ranges (R H , R A ).

Abstract translation: 一种用于进行核酸扩增的方法，包括提供在相应位置容纳核酸探针（37）的阵列（36）的反应室（31），用于与各自的靶核酸杂交; 以及将溶液（50）引入所述反应室（31）中，其中所述溶液（50）含有能够结合靶核酸，核苷酸，核酸延伸酶和包含核酸的样品的引物。 核酸探针（37）的结构和引物的结构使得探针（37）的杂交温度（TH）高于引物的退火温度（TA），由此在各自的条件下进行杂交和退火 分开的温度范围（RH，RA）。

公开(公告)号：WO2010057808A1

公开(公告)日：2010-05-27

申请号：PCT/EP2009/064918

申请日：2009-11-10

Applicant: STMicroelectronics (GRENOBLE) SAS ,  STMicroelectronics S.r.l. ,  COFFY, Romain ,  BRECHIGNAC, Rémi ,  COGNETTI DE MARTIIS, Carlo

Inventor： COFFY, Romain ,  BRECHIGNAC, Rémi ,  COGNETTI DE MARTIIS, Carlo

IPC: H01L25/16 ,  H01L23/538 ,  H01L21/60

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2224/0401

Abstract: A semiconductor device includes at least one first component (5) (for example, a first integrated circuit), having a front face provided with electrical connection pads. The first component is embedded in a support layer (2) is a position such that the front face of the first component is not covered and lies parallel to a first face of the support layer. An intermediate layer (8) is formed on the front face of the first component and on the first face of the support layer. An electrical connection network (9) within the intermediate layer selectively connects to the electrical connection pads of the first component. The device further includes at least one second component (11) (for example, a second integrate circuit, having one face placed above the intermediate layer and provided with electrical connection pads selectively connected to the electrical connection network. Electrical connection vias (17) pass through the support layer and selectively connect the electrical connection network to an external electrical connection formed on a second face of the support layer.

Abstract translation: 半导体器件包括至少一个第一部件（5）（例如，第一集成电路），其具有设置有电连接焊盘的正面。 第一部件嵌入在支撑层（2）中，是使得第一部件的前表面不被覆盖并平行于支撑层的第一面的位置。 在第一部件的正面和支撑层的第一面上形成中间层（8）。 中间层内的电连接网络（9）选择性地连接到第一部件的电连接焊盘。 该装置还包括至少一个第二部件（11）（例如，第二集成电路，其中一个面放置在中间层的上方，并且具有选择性地连接到电连接网络的电连接焊盘）。电连接通孔（17）通过 通过支撑层并且将电连接网络选择性地连接到形成在支撑层的第二面上的外部电连接。

公开(公告)号：WO2009080760A1

公开(公告)日：2009-07-02

申请号：PCT/EP2008/068047

申请日：2008-12-19

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: G01R1/073

CPC classification number: G01R31/2889 ,  B62M25/04 ,  G01R1/0491 ,  G01R1/06727 ,  G01R1/07342

Abstract: A probe card (105') adapted for testing at least one integrated circuit integrated on corresponding at least one die (145) of a semiconductor material wafer, the probe card including a board (125') adapted for the coupling to a tester apparatus, and a plurality of probes (225) coupled to the said board, wherein the probe card comprises a plurality of replaceable elementary units (135'), each one comprising at least one of said probes for contacting externally-accessible terminals of an integrated circuit under test (145), the plurality of replaceable elementary units being arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested.

Abstract translation: 一种探针卡（105'），适用于测试集成在半导体材料晶片的相应的至少一个管芯（145）上的至少一个集成电路，所述探针卡包括适于耦合到测试仪器的板（125'）， 以及耦合到所述板的多个探针（225），其中所述探针卡包括多个可更换的基本单元（135'），每个所述探针卡包括至少一个所述探针，用于接触集成电路的外部可接近的端子 所述多个可更换基本单元被布置成对应于包含要测试的集成电路的半导体材料晶片上的至少一个管芯的布置。

公开(公告)号：WO2008136028A1

公开(公告)日：2008-11-13

申请号：PCT/IT2007/000338

申请日：2007-05-08

Applicant: STMICROELECTRONICS S.R.L. ,  TORAZZINA, Aldo ,  RUSSO, Riccardo

Inventor： TORAZZINA, Aldo ,  RUSSO, Riccardo

IPC: H04L12/10

CPC classification number: G01R27/08 ,  G06F1/26 ,  H04L12/10

Abstract: PDs that can be supplied through the LAN line are discriminated from PDs that cannot be so supplied in function of the resistance of the supply line and of the voltage drop Vdrop caused by nonlinear elements in series therewith. The values of these two parameters are estimated by applying two distinct voltages to the supply terminals of the LAN line and sensing the relative steady-state currents absorbed by the power supply line and by processing voltage and current values for estimating the resistance (Rdet) of the line and the voltage drop (Vdrop) caused by nonlinear elements connected in series therewith.

Abstract translation: 可以通过LAN线提供的PD与由供应线的电阻和由与其串联的非线性元件引起的电压降Vdrop不能如此提供的PD进行区分。 通过将两个不同的电压施加到LAN线路的电源端子并且感测由电源线吸收的相对稳态电流以及通过处理电压和电流值来估计这两个参数的值来估计电阻（Rdet）的电阻 由与串联连接的非线性元件引起的线路和电压降（Vdrop）。

公开(公告)号：WO2008012845A1

公开(公告)日：2008-01-31

申请号：PCT/IT2006/000575

申请日：2006-07-26

Applicant: STMICROELECTRONICS S.R.L. ,  CONOCI, Sabrina ,  PETRALIA, Salvatore ,  SORTINO, Salvatore

Inventor： CONOCI, Sabrina ,  PETRALIA, Salvatore ,  SORTINO, Salvatore

IPC: C01B21/24 ,  A61K33/00 ,  B01J19/12

CPC classification number: C07C211/52 ,  A61K31/04 ,  A61K33/00 ,  B01J19/123 ,  B01J2219/089 ,  C01B21/24 ,  C07C323/29 ,  A61K2300/00

Abstract: The present invention- relates to the use of a nitroaniline derivative of Formula I for the production of nitric oxide and for the preparation of a medicament for the treatment of a disease wherein the administration of nitric oxide is beneficial. The present invention furthermore relates to a method for the production of NO irradiating a nitroaniline derivative of Formula I, a kit comprising a nitroaniline derivative of Formula I and a carrier and to a system comprising a source of radiations and a container associated to a nitroaniline derivative of Formula I. In Formula I, R and R I are each independently hydrogen or a C 1 -C 3 alkyl group; R II is hydrogen or an alkyl group.

Abstract translation: 本发明涉及式I的硝基苯胺衍生物在制备一氧化氮中的用途，以及制备用于治疗一氧化氮是有益的疾病的药物的用途。 本发明还涉及一种用于制备辐射式I的硝基苯胺衍生物的NO的方法，该试剂盒包含式I的硝基苯胺衍生物和载体，以及包含辐射源和与硝基苯胺衍生物相关的容器的体系 在式I中，R 1和R 2各自独立地为氢或C 1 -C 3烷基; R II是氢或烷基。

公开(公告)号：WO2008010007A1

公开(公告)日：2008-01-24

申请号：PCT/IB2006/002032

申请日：2006-07-19

Applicant: STMICROELECTRONICS S.R.L. ,  CONVERTINO, Gabriella ,  PARATA, Carlo ,  SCARPA, Vincenzo

Inventor： CONVERTINO, Gabriella ,  PARATA, Carlo ,  SCARPA, Vincenzo

IPC: H04L12/28

CPC classification number: H04W76/043 ,  H04W72/04 ,  H04W76/11 ,  H04W76/15 ,  H04W76/23 ,  H04W84/12

Abstract: A wireless communication network, such as a IEEE 802.11 WLAN, includes an access point (AP) and a plurality of stations (STAl, STA2). The Access Point (AP) sends towards the stations (STAl, STA2) periodic information arranged in time frames or beacon intervals. The stations (STAl, STA2) in the network are configured to communicate: - in a first mode, called Infrastructure Mode (IM), through the access point (AP), and - in a second mode, called Direct Link Mode (DLM), directly with each other. The time frames are partitioned into: - a first time interval (IM_SI) wherein the stations (STAl, STA2) communicate in the first mode over a first channel; - a second time interval (DLM_SI) wherein the stations (STAl, STA2) communicate in the second mode over a second channel/ and - a third time interval (MIXED_SI) wherein the stations (STAl, STA2) communicate in either of the first (IM) or the second (DLM) mode.

Abstract translation: 诸如IEEE 802.11 WLAN的无线通信网络包括接入点（AP）和多个站（STA1，STA2）。 接入点（AP）向站点（STA1，STA2）发送以时间帧或信标间隔排列的周期性信息。 网络中的站（STA1，STA2）被配置为通信： - 在第一模式中，通过接入点（AP）称为基础设施模式（IM），以及 - 在称为直接链路模式（DLM）的第二模式中， ，直接对方。 时间帧被划分为： - 第一时间间隔（IM_SI），其中站（STA1，STA2）通过第一信道以第一模式通信; - 第二时间间隔（DLM_SI），其中站（STA1，STA2）在第二模式中通过第二信道/和第三时间间隔（MIXED_SI）进行通信，其中站（STA1，STA2）在第一（ IM）或第二（DLM）模式。

公开(公告)号：WO2007148354A1

公开(公告)日：2007-12-27

申请号：PCT/IT2006/000476

申请日：2006-06-21

Applicant: STMICROELECTRONICS S.R.L. ,  ADRAGNA, Claudio ,  GATTAVARI, Giuseppe

Inventor： ADRAGNA, Claudio ,  GATTAVARI, Giuseppe

IPC: H02J1/10 ,  H02M3/158

CPC classification number: H02M3/1584 ,  H02J1/102 ,  H02M2001/0048 ,  Y02B70/1491 ,  Y10T307/406 ,  Y10T307/555 ,  Y10T307/707

Abstract: A control device of a plurality of switching converters (Convl.ConvN) is disclosed; each converter comprises at least one power switch and is associated with a control circuit (Mod1 ...ModN) of the at least one power switch. The control device comprises means (100) suitable for comparing a signal (CTRL) representative of the load of the plurality of converters (ConvL.ConvN) with a plurality of reference signals (Vref1 ...Vref(N-l)) and suitable for enabling or disabling at least one of said plurality of control circuits (Mod1...ModN) in response to said comparison.

Abstract translation: 公开了多个开关转换器（Convl.ConvN）的控制装置; 每个转换器包括至少一个电源开关并与所述至少一个电源开关的控制电路（Mod1 ... ModN）相关联。 控制装置包括适于将表示多个转换器（ConvL.ConvN）的负载的信号（CTRL）与多个参考信号（Vref1 ... Vref（N1））进行比较并且适合于使能的装置（100） 或者响应于所述比较而禁用所述多个控制电路（Mod1 ... ModN）中的至少一个。

公开(公告)号：WO2007135694A1

公开(公告)日：2007-11-29

申请号：PCT/IT2006/000372

申请日：2006-05-18

Applicant: STMICROELECTRONICS S.R.L. ,  RONSISVALLE, Cesare ,  ENEA, Vincenzo

Inventor： RONSISVALLE, Cesare ,  ENEA, Vincenzo

IPC: H01L29/745 ,  H01L29/749 ,  H01L29/74

CPC classification number: H01L29/7395 ,  H01L29/742 ,  H01L29/7455

Abstract: Described herein is a power device (10) having a first current-conduction terminal (A) , a second current-conduction terminal (K) , a control terminal (G) receiving, in use, a control voltage (VGATE) of the power device (10), and a thyristor device (12) and a first insulated-gate switch device (14) connected in series between the first and the second conduction terminals; the first insulated-gate switch device (14) has a gate terminal connected to the control terminal (G), and the thyristor device (12) has a base terminal (16) . The power device (10) is further provided with: a second insulated-gate switch device (18), connected between the first current-conduction terminal (A) and the base terminal (16) of the thyristor device (12) , and having a respective gate terminal connected to the control terminal (G) ; and a Zener diode (19) , connected between the base terminal (16) of the thyristor device (12) and the second current-conduction terminal (K) so as to enable extraction of current from the base terminal (16) in a given operating condition.

Abstract translation: 这里描述的是具有第一通电端子（A），第二通电端子（K），控制端子（G）的功率器件（10），其在使用中接收功率的控制电压（VGATE） 装置（10）和串联连接在第一和第二导电端子之间的晶闸管装置（12）和第一绝缘栅极开关装置（14） 第一绝缘栅极开关装置（14）具有连接到控制端子（G）的栅极端子，并且晶闸管装置（12）具有基极端子（16）。 功率器件（10）还具有连接在晶闸管器件（12）的第一通电端子（A）和基极端子（16）之间的第二绝缘栅极开关器件（18），并具有 连接到所述控制端子（G）的相应的栅极端子; 和连接在晶闸管器件（12）的基极端子（16）和第二通电端子（K）之间的齐纳二极管（19），以便能够在给定的基极端子（16）中提取电流 操作条件。

公开(公告)号：WO2007116420A1

公开(公告)日：2007-10-18

申请号：PCT/IT2006/000244

申请日：2006-04-11

Applicant: STMICROELECTRONICS S.R.L. ,  LORENTI, Simona ,  CAMALLERI, Cateno Marco ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

Inventor： LORENTI, Simona ,  CAMALLERI, Cateno Marco ,  SAGGIO, Mario, Giuseppe ,  FRISINA, Ferruccio

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/336 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/10 ,  H01L29/739 ,  H01L29/732

CPC classification number: H01L21/3247 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/324 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/73 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8611 ,  H01L29/872

Abstract: Process for manufacturing a semiconductor power device, wherein a trench (8) is formed in a semiconductor body (2) having a first conductivity type; the trench is annealed for shaping purpose (8a) ; and the trench (8a) is filled with semiconductor material via epitaxial growth so as to obtain a first column (9) having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases .

Abstract translation: 一种制造半导体功率器件的方法，其中在具有第一导电类型的半导体本体（2）中形成沟槽（8） 沟槽退火成型目的（8a）; 并且沟槽（8a）通过外延生长填充半导体材料，从而获得具有第二导电类型的第一列（9）。 外延生长通过在卤化物气体的存在下供给包含硅和含有第二导电类型的掺杂剂离子的气体进行，并且以掺杂剂离子的均匀分布发生。 含气体掺杂剂离子的流动在外延生长期间根据线性斜坡而变化; 特别是在硬掩模存在下选择性地生长半导体材料的情况下，流量减少; 在非选择性生长的情况下，在没有硬掩模的情况下，流动增加。

公开(公告)号：WO2007096913A1

公开(公告)日：2007-08-30

申请号：PCT/IT2006/000104

申请日：2006-02-24

Applicant: STMICROELECTRONICS S.R.L. ,  DALLAVALLE, Carlo ,  CONIGLIARO, Salvatore

Inventor： DALLAVALLE, Carlo ,  CONIGLIARO, Salvatore

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  H01L27/11803

Abstract: The present invention relates to a method for designing a complex circuit architecture (1) including a plurality of circuit portions interconnected one to the other in said architecture, each circuit portions including a VLSI number of on-board transistors of both NMOS and PMOS type and wherein a circuit architecture core (2) is associated to at least a couple of body bias generators (3), one for said NMOS and one for said PMOS transistors; characterized by the following steps: - providing said circuit architecture core by a library of basic transistor cells having N and P MOS substrates separated from their corresponding source terminals; - monitoring the active current (Ion) in said transistors; - comparing the monitored current with a predetermined current value corresponding to standard or typical working conditions of said transistors according to the result of the comparison phase providing a reverse bias for those cells of the circuit architecture core to be compensated because of a possible excess of current leakage.

Abstract translation: 本发明涉及一种用于设计包括在所述架构中彼此相互互连的多个电路部分的复合电路架构（1）的方法，每个电路部分包括VLSI数量的NMOS和PMOS型的板上晶体管，以及 其中电路架构核心（2）与至少一对主体偏置发生器（3）相关联，一个用于所述NMOS，一个用于所述PMOS晶体管; 其特征在于以下步骤： - 通过具有从其对应的源极端子分离的N和P MOS衬底的基本晶体管单元库提供所述电路架构内核; - 监测所述晶体管中的有功电流（Ion）; - 根据比较结果的结果，将所监视的电流与对应于所述晶体管的标准或典型工作条件的预定电流值进行比较，为由于可能的过电流而补偿的要补偿的电路架构核心的那些单元提供反向偏置 泄漏。